PIC vs ARM assembler (no flamewar please)

I was recently visited by the Renesas sales force in spite of being told I would be using an ARM part... they were very persistent and I decided the best way to chase them off was to let them try to sell me for a half hour or so. I listened to their spiel and started asking questions. A lot of them had to do with what is the difference between this part and that part, or this group and that group, or this family and that family... They started apologizing and admited that they product line was a bit chaotic. When I had looked at their parts for a design four years ago I had the hardest time even figuring out what they made! Every part was a separately presented design and you had to download the data sheet and read it all to figure out what it had. It was like the company never considered that there might be similarities between different parts. I never did figure out what they meant by "group" and "family"... I still don't know.

Anyway, I haven't heard from the sales force for a couple of weeks. Once I pick an ARM part I may let them go head to head with it and see how they do.

meddelandetnews: snipped-for-privacy@v33g2000cwv.googlegroups.com...

Yeah, but how many days does it take to execute?

;^)

What a coincidence: that's the other micro I'm currently using. Some of the instructions can get pretty long in an H8, but the assembly language generated by a compiler is a joy to behold.

Definitely. When I was in grad school I took a 3-credit "microprocessor architecture" class which consisted almost entirely of comparing three 32-bit processor architecture: IA32, 68K, and 32K. Everybody in the class gave a presentation comparing one particular aspect of the three.

The 32000 was definitely the winner (though I've heard unpleasant stories about bugs and support). The 68K was a definite second place, and the IA32 was seventh.

Are we getting ready to fight the RISC/CISC wars again? I'll take a ringside seat! :)

Elegance is not quite everything - and that instruction is not elegant. I don't have a problem with a processor taking three or four instructions to code an operation like that - on most cpus where you can have complex addressing modes, the instructions take many clock cycles and many instruction words, and could therefore be easily split into several instructions. I dislike architectures where you need several instructions to do the simplest of things, like loading a register with a constant, but I see no benefit in trying to do everything possible within a single instruction.

Seventh out of three? Nice comparison...

That's to be expected - the MSP430 is quite an old design, IIRC coming from Germany and targeting firstly ROM devices for low power systems. It will have pre-dated C compilers.

I see they now offer extended address reach in the MSP430.

-jg

That's news to me. The MSP430 family was announced with great fanfare by TI just a few years ago. Are you saying they are based on somebody else's older design?

Roberto Waltman

What?!?! C compilers have been around for 30 years. The MSP430 has been around for what, 5 or 6 years?

I knew after I wrote that, that I should have used more words... :)

- I meant the MSP430 Silicon was designed before they had a C compiler for the microcontroller. Clearly C technology itself is much older.

It's the trendy thing these days to claim your core was 'Designed for C', but often that's just marketing spin.

-jg

The flash version is relatively new, but the mask models go way-back.

-jg

Hell, Jim, Lutz Bierl is SLAA024.PDF claims the MSP430 is RISC! Now, that's spin, indeed.

Jon

I liked what I saw in the 32032, early on. Never did get a chance to actually use one. I also liked the 88k, around that time. Never actually used one of those, either, though. Still have manuals floating around here for both families, though.

The 88k had an odd 'selling point' they made -- you could bond one CPU on top of another, all pins except just one to indicate which CPU was to observe and which was to actually work, and the monitoring CPU would duplicate all operations and signal an error if it ever decided that the working CPU did something different. :)

Jon

Yea, I argued with the FAE about that claim at the last MSP430-day seminar thing. He also claimed that it was a "one clock per isntruction" design.

I think you misspelled "lying". ;)

Nice feature _if_ you have the luxury to put the system into "safe mode" when there is a disagreement.

Paul

The application that came immediately to mind was use in space, such as on satellites or mars missions, to detect soft errors.

Jon

The ARM design is unusual for a RISC in being three-address and having conditional execution of nearly all its instruc- tions. This tends to waste 8 bits of every 32-bit instruc- tion. Surely, they could have found better uses for those bits [and don't call me Shirley, "Airplane", ca. 1970].

Also these instructions could be scheduled out of a loop, or interleaved with other instructions so that they execute faster than any complex instruction.

Some of this can be alleviated with smart assemblers. There is no hard and fast rule that says an assembler must produce a single instruction for each mnemonic. Simple instruction selection and expansion are commonly featured in assemblers.

I'm curious what better use you have for those 8 bits? Another 8 bits are "wasted" on the shifter for example, so you could save 16 bits per instruction. The result is... Thumb.

But since 16-bit instructions do less (3 operands, shifts and conditional execution are quite common), Thumb needs around 30% more instructions to do the same amount of work as ARM.

Thumb-2 introduces the IT instruction which makes the following 1-4 instructions conditional. This form of conditional execution wastes fewer bits overall eventhough it uses more bits per conditional instruction (it is still smaller and faster than using branches of course).

Wilco