Yeah, I got all that but I just wonder why they bothered with that design to start with?
The ARM chips I have dealt with, all you lost when messing up any PLL setup was the DRAM interface.
Ah, thanks.
-- Les Cargill
It may be a flaw, but if so it's an intentional one. The behavior is shared by all the ARM Cortex parts that I've used, both from Luminary/TI and from ST.
-- www.wescottdesign.com
As far as I know, the JTAG is a part of the core design coming as a block from ARM to the sublicensees. The documentation is very careful about the details, but my guess is that the whole core block is synthetized synchronous logic, running on the core clock. There is a hint about it, when it is said that one should not use the WFI (wait for interrupt) instruction, if it is desired to debug with JTAG.
-- -TV
I can't remember the wording, but I felt that the verbiage surrounding the WFI instruction stuff was more than a hint.
And the WFI does, indeed, royally screw JTAG. I do kinda wish that ARM had built something in so to detect activity on the JTAG port and flip a bit -- it would be nice to sense the presense of JTAG and refrain from using the WFI instruction.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Or just pick the clock to the JTAG part ahead of the WFI gating.
The best would be to follow the schematics in the JTAG standard and just clock that part from TCK alone.
-- -TV
Well, I suppose if I'm wishing -- yes. But from TCK please -- WFI is there to minimize power consumption, which is kinda hard if you have some obligate clocked portion of the chip.
I'm thinking maybe I'll build something into the software to run for five minutes or so without WFI, and then enable it if some bit somewhere isn't set. That'll let JTAG come up in "human time".
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
it is more complicated than that, (it's been 10+ year since I worked on ARM but..) all then boundary scan etc. works just fine, but everything that talk to the CPU is sampled with cpu clk to avoid the async clock, that is also the reason for rclk which is just the tck sampled with clock
talking to the cpu is mostly handfeeding data and enabling a single clock cycle
-Lasse
At least on the 1768/69 the wfi shuts down *some* DMA transfers. This caught me when I moved a buffer to the main memory block in my linker script:
"The GPDMA may operate in Sleep mode to access AHB SRAMs and peripherals with GPDMA support, but the GPDMA cannot access the flash memory or the main SRAM, which are disabled in order to save power."
Also happens if you build a DMA chain where some of the transfer is const text in flash.
You will be waiting on the DMA interrupt until your WDT goes off.
-- Chisolm Republic of Texas
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