Hi,
I have some queries based on the MPU Clock/Reset/Power Mode Control Registers of OMAP 5912 and 5910.
Does the term "OMAP 3.2 hardware engine" mentioned in OMAP 5912 technical document refer to the term "DSP" mentioned in OMAP 5910 technical document.
Pls find the snapshot of the info :
In OMAP 5912 ============= ARM_RSTCT1 - MPU Reset Control 1 Register . This is a 32-bit register.
Bit 3 - If set, Resets the OMAP 3.2 hardware engine. Once set to logic
1 by the MPU core processor, this bit returns to logic 0 on the next cycle.Bit 0 - If set, Resets the MPU core. Once set to 1 by the MPU core, this bit returns to 0 on the next cycle.
In the case of OMAP 5910 ======================
ARM_RSTCT1 - Initiates the S/W reset to the MPU and DSP . THis is a
16-bit register.Bit 3 - If set, Resets the DSP, MPU, and peripherals (the bit is always read 0):
Bit 0 - If set, Resets the MPU . Once set to 1 by the MPU core, this bit returns to 0 on the next cycle.
Thx in advans, Karthik Balaguru