Multicycle Instruction Overlapping

No, you don't. You must learn that the above statement means that you must not, under any circumstances, assume anything about the exact internal proceedings in that situation.

There are questions you're actually better off not knowing the answer to. The above would be one of them.

Interesting reply. Actually I am new to this level of study. I read it through some text. So in case if it can be done in some way that can simply because integer ALU and Floating Point Unit are different resources and hence can be used in parallel.

But the implementation can be different depending upon architecture. Is it this you wanted to say ?

Regards Ripunjay Tripathi

Since in RISC you can't assume an offset for all instructions on the same level of indirection, you cannot assume any further level of indirection for which the memory operation is buffered, because it would take the same time to return as it would to add to that level of indirection, an offset in which the memory operation is implied by a subsequent memory operation or add. There are other cases however in which the transfer circuitry between logical processor units can be meta-synchronous with the same levels for which a wire protocol exists for the memory wherefore, using an add macro, the operation can be broken up over multiple transfer cycles. This would require an external timer to punch the capacitance across the edge-level if the transfer operation is specified by the protocol, and you can add to the observer for which the memory is privileged in the same time, either log:user or exp:supervisor since the page must be double checked per user if the timer is to remain consistent with the internal circuitry, a co-variant optimization like-wise. See:

Patrick Ashley Meuser"-Bianca" Cyberneticist