We built ours
Stephen
-- Stephen Pelc, stephenXXX@mpeforth.com MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeforth.com - free VFX Forth downloads
Since you are targeting JTAG, I'd suggest a simple Compression wrapper on the USB link. The JTAG clock data has to be uncompressed, but you can stream the USB data compressed, and that will remove any USB bottleneck. - and it is the long datastreams that will benefit the most from compression.
So, target a device with good DMA into largish RAM blocks, and with the fastest possible SPI CLK speeds. USB -> DMA -> Packed RAM PackedRam => CPU Unpack => UnpackedRAM UnpackedRAM -> DMA -> SPI/SSC
Ulf can probably help with the details :)
-jg
It's not always so simple. I have an ARM chip with a slow Jtag/debug wire. Fast USB datastreams would overrun the ARM state machine. I have to slow down the USB side just to avoid overrunning the ARM chip.
Of course, I'd expect any half-decent implementation to allow control of the JTAG clock speed, and to have handshakes so that any JTAG clock speed was supported. A smarter system might even allow block-setable JTAG speeds, and even a CPLD to fan-out the JTAG, so that systems might have a FAST and SLOW jtag branches.
Mostly I was focusing on getting the highest possible streaming speed, on a std system. Once you have that, it's pretty trivial to slow it down later :)
-jg
Altera NIOS with external FLASH and RAM will meet your requirements.
George
"GMM50" skrev i meddelandet news: snipped-for-privacy@c77g2000hse.googlegroups.com...
And is also going to more expensive, use more power etc. Does the Altera FPGAs have a High Speed USB interface? Was not aware of that!
-- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
The fact is, I am getting more clarity into the requirement with all the valuable comments ! im yet to look at jtagwidget..
the "device" intended, must be low cost : just a little more than a wiggler.
ease of use and robustness is important : if it runs off the usb power all the more better !
finally it must support an entire family of devices with same debug interface like arm7 series or arm9series with 14pin or 20 pin etc
the "device" will have highlevel protocol which will translate a single message into a a set of JTAG commands. that is not simply a data redirector.
i suppose many commercial implementations already do this, but..at low cost..?
Kind Regards, Ravishankar
PS: henceforth i have answer from another id...
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