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LH75401 + 800x600 colorTFT

Hello I am beginner using arm CPU-s. And I have problem with my controller. Problem is I get 12 copys horizontaly, but vertical works fine. It seems that it only displays data wich is in DMA fifo. Some strange reason it reads frame buffer verticaly but not whil "printing" horizontal line

Allos some strange things

1) in user manual LCD Upper Panel Base Address register have to reserve bits so i need to shift, but actually it is not necessary, otherwize i never work 2) register Clocks_Per_Line : In datasheet Clocks_Per_Line = Pixels_Per_Lin

-1. Pixels_Per_Line = (actual pixsels per line/16)-1. But wh Clocks_Per_Line register is 10 bits?

my LCD code:

const long Horisontal_Back_Proch = 128 ; // const long Horisontal_Front_Proch = 24 ; // const long Horizontal_Sync_Pulse_Width = 72 ; // const long Pixels_Per_Line = 800 ; //

const long Vertical_Back_Porch = 22 ; // const long Vertical_Front_Porch = 1 ; // const long Vertical_Sync_Pulse_Width = 2 ; // const long Lines_Per_Panel = 600 ;

const long Bypass_Pixel_Clock_Divider = 1 ; const long Clocks_Per_Line = 799; const long Invert_Output_Enable = 0 ; const long Invert_Panel_Clock = 1 ; const long Invert_Horizontal_Sync = 1 ; const long Invert_Vertical_Sync = 1 ; const long AC_Bias_Pin_Frequency = 0 ; const long Panel_Clock_Divisor = 1 ;

const long LCD_Upper_Panel_Base_Address = 0x04000000; const long LCD_DMA_FIFO_Watermark_Level = 1 ; const long LCD_DMA_FIFO_Test_Mode_Enable = 0 ; const long LCD_Vertical_Compare = 0 ; const long LCD_Power_Enable = 1 ; const long RGB_or_BGR_Format_Selection = 1 ; const long LCD_Interface_is_Dual_Panel_STN = 0 ; const long Monochrome_LCD = 1 ; const long LCD_is_TFT = 1 ; const long STN_LCD_is_Monochrome = 0 ; const long LCD_Bits_per_Pixel = 4 ; const long LCD_Controller_Enable = 1 ;

void LCD_INIT(void){

LCDUPBASE = LCD_Upper_Panel_Base_Address ;//

Reply to
murphy86
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I'm guessing that you are exceeeding the memory bandwidth so that the fifi is underflowing. There are status bits for this sort of thing. During the line sync it may get enough time to load the fifo. I can't reproduce this on my system (75411) because my panel is 320x240x2bpp which doesn't need that much bandwidth - I even set the memory wait states to max.

What makes you think that. The two reserved bits are zero because the panel addresses have to be 32-bit alligned, while the register takes a byte address for convenience (in C/C++ at least).

Try slowing down the pixel clock. It will cause flickering, but if the display data looks good then underrun looks like the culprit.

[snipped code]

Peter

Reply to
Peter Dickerson

fifi

on

that

yes it seems so that allso explaned that DMA FIFO underfollow bitt, i go it working but 12hz refresh rate. Allso in need to option to display dat on CRT (usin D/A converter) i need 33Mhz piksel clk for that. Anyway solver problem using xilinx FPGA(xc2s50). It disconects graphic memor form bus while cpu is not using it and copys data from memory into two 4 fifos (ftd7204) so i can get 15 bit colors (optimal for memory). If somebody wants code for fpga and schematic and pcb layout send email t snipped-for-privacy@hot.ee and i send project files.note that xilinx ISE webpack i free software until you not sell product and conection cable is easy t make(needed only one 74hc244 chip).

it

panel

because 2 lowest bit are reserved.

Pixels_Per_Line

Reply to
murphy86

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