FX2LP I/O port issue... need help

Mar 20, 2010 0 Replies

Good evening all. My design has a chip connected to a FX2LP ( 100 pins). The firmware, written and compiled with SDCC, works except access to the E port...


I've tried several stuffs, like putting my "toggling code" into existing code and came to the conclusion that something is missing in my initialization code. In clear : I am not able to read or write to port E. An oscilloscope connected to any of the 8 pins doesn't show anyhting, pin stay "silent".


The code below is what remains after removing everything not related to the issue... and doesn't work :-(


If any of you has the "good eye" and can tell me what I've missed... that would help ;-)


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#define ALLOCATE_EXTERN #include "include/fx2regs.h"


#define SYNCDELAY _asm \ nop; \ nop; \ nop; \ nop; \ nop; \ nop; \ nop; \ _endasm; static void Initialize(void) { CPUCS=0x12; // 48 MHz, CLKOUT output enabled. IFCONFIG=0xc0; SYNCDELAY; // Internal IFCLK, 48MHz; A,B as normal ports.



CKCON &= ~7; EXIF &= ~16; REVCTL=0x03; SYNCDELAY; // See TRM...



OEA = OEB = OED = 0xff; SYNCDELAY; IOA = IOB = IOD = 0xff; SYNCDELAY; OEA = OEB = OED = 0xff; SYNCDELAY; IOA = IOB = IOD = 0x00; SYNCDELAY;



EP6CFG=0xe2; SYNCDELAY; // 1110 0010 (bulk IN, 512 bytes, double-buffered)



FIFORESET=0x80; SYNCDELAY; // NAK all requests from host. FIFORESET=0x82; SYNCDELAY; // Reset individual EP (2,4,6,8) FIFORESET=0x84; SYNCDELAY; FIFORESET=0x86; SYNCDELAY; FIFORESET=0x88; SYNCDELAY; FIFORESET=0x00; SYNCDELAY; // Resume normal operation. }


void main(void) { Initialize();



PORTACFG = 0 ; PORTCCFG = 0 ; PORTECFG = 0 ; // disable all alternate functions on port E SYNCDELAY; IOE = 0x00 ; // OEE = 0xff ; // all pins are outputs SYNCDELAY;



while( 1 ) { SYNCDELAY; IOE = 0xff ; // all pins should be 1 SYNCDELAY IOE = 0x00 ; // all pins should be 0 } }



==== Can't see anything on port E... thanks


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