FEC - Forward Error Correction on a PIC? - Page 2

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Re: FEC - Forward Error Correction on a PIC?


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No problem. You can certainly implement some relatively simple FEC on
PIC.
Take a look at our web site for examples.


Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

http://www.abvolt.com

Re: FEC - Forward Error Correction on a PIC?

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error


I am sorry to complain about a fine showing of replies, but my main worry is
not the implementation of the fec, but rather how do you receive a
bitstream.  How do you synchronise the receiver so that its bit centres are
aligned with the tx station.  Oversampling seems a way to go, maybe
oversample by 8 times and use those 8 samples to work out where the leading
edges of the bits are.  This could be constantly fed as a bias to the timer
so that the rx & tx clocks are aligned.  This I guess would also allow for a
drift between the two frequencies.

Thanks again

Marky C



Re: FEC - Forward Error Correction on a PIC?
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The usual method is to initially sample at some submultiple of the
bit period, ideally odd, but usually even.  Say the multiple is
7.  You can detect the start bit either by an interrupt on the
bit, or by sampling on clock intervals.  You now wait 3 units and
resample to confirm the start bit.  From there on you resample at
7 units, putting the samples at the nominal bit centers.  The stop
bit is detected at the center point, i.e. 1/2 bit time, and the
system resets.  If the stop bit is missing you have either a
framing error or a break, depending on the previous bits, and must
wait for a true stop before continuing.

The most common multiple used is 16, which is why UART chips
normally require baud clocks at 16x.

--
Chuck F ( snipped-for-privacy@yahoo.com) ( snipped-for-privacy@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
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Re: FEC - Forward Error Correction on a PIC?

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   Async receiving is of course an essential task in this app, but
it's not (too) complicated. The receiver 'clock' doesn't need to start
until one sees the leading edge of the start bit. You shouldn't need
to detect the edges of the other bits (depending on the data, those
edges may not be there anyway). If the last data and stop bits don't
happen in the 'window' you're looking at, then the incoming data is
clocked at a frequency that's out of spec or at the wrong baud rate.
The first data bit is sampled at 1.5 bit times after the start bit's
leading edge, the second bit at 2.5 bit times, etc. For higher
reliability, using the 8-samples-per-bit time, you can sample at three
places in the middle of the bit time, and decide that the received bit
is the value of the majority of bits. I recall reading the data sheet
for an old hardware UART that receives this way. Here's a diagram of
the idea, where | is the bit edge time, and * is a sample time:

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
|     * * *     |     * * *     ...

   The async transmitter should operate on its own independent 'clock'
that gives the proper baud rate. It's much easier than the receiver.

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Re: FEC - Forward Error Correction on a PIC?
Well thanks for all your replies.  I now feel that a PIC is up to the job, I
will have to get off my behind and write some code.

Thanks,

Marky C



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