Hello,
I wanted to inquire if someone else has seen this kind of phenomenon before...
I have a design (currently implemented in an FPGA) which drives a CompactFlash from a microcontroller, specifically a T80 (Z80 clone) from opencores.org, with my own firmware. The clock frequency is
25 MHz.The weird part is that it reads all cards fine, but when it comes to writing I get some extremely odd behaviour. I have two cards -- a 64 MB card from IOData and a 128 MB card from SanDisk, both used but which write fine in a PC -- very quickly giving me an unrecoverable error on write, with the error register set to either 81h or 40h. The failing sector is filled with garbage which doesn't look random; it has a lot of 55h bytes in particular. Furthermore, the sectors
*after* the failing sector, up to the next 4K boundary, is filled with a 16-bit pattern, usually, but not always, 0Fh 80h.Occationally, too, I see entire 512-byte sectors filled with zero without an error being reported. After those, normal operation resumes fine with the next sector.
However, a brand new card, 256 MB from POI, works like a charm.
It just seems very odd to me. I'm mostly a software guy, so the hardware aspects of this project are largely new to me. However, I have tried to eliminate glitches or asynchronicities. The board is the Altera NIOS development kit, so I have no reason to believe the electricals are marginal as I might have if it had been a custom board. However, part of the reason I'd like to understand the phenomenon is that I might want to use this design as a prototype for a "real" hardware project in the future.
Detailed info (read only if bored):
It uses the 8-bit common memory mode of CompactFlash, reading/writing single sectors at a time, in LBA mode. The timing of the signals is as follows (1 cycle = 40 ns):
- A/Dout latched at the same time CE1# is asserted, so they should be stable for the duration of the transfer 1 cycle - CE1# asserted, WE/OE# deasserted 3 cycles - CE1# asserted, WE/OE# asserted -> WAIT# sampled during this time; if WAIT# is sampled low within 2 cycles of WE/OE# assertion, the access will be held until at least 1 cycle after WAIT# deassertion - Din latched at the same time OE# is deasserted 2 cycles - CE1# asserted, WE/OE# deasserted
After sending a command, the firmware will wait for BSY# assert and deassert; the pulse is latched in hardware and then polled by firmware.
I have not actually seen WAIT# being asserted by any card that I have tried.
The source code (Verilog) is part of the project at:
ftp://ftp.zytor.com/pub/fpga/abc80/abc80-10.zip
Thanks!
-hpa