Cache miss cycles

In an older paper I've read that instruction cache misses can take up to

100 cycles in which the cache gets refilled. What are typical I-cache miss cycles for today's DSPs employed in embedded systems? Can you give me some examples for some specific processors?


Reply to
Stephan Ceram
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There is no answer to this question, as it can vary so wildly. Differentiating factors include the speed of the processor, the speed and latency of the memory, contention for the memory buses, the types of cache, the associativity of the cache, and the type of code that is running. Add to that mix the latency of branch misprediction (which is often associated with cache misses) which varies hugely according to the processor, and you have an cycle costs varying from about 2 to 200.

Reply to
David Brown

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