ATMEL EEPROM endurance?

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Hi,

I'm using an ATMega128 chip and it says that it's EEPROM has an
endurance of 100,000 write/erase cycles. What exactly does this mean?
Does this mean it'll stop working after 100,000 write/erase cycles in
whole or does that mean it can do 100,000 write/erase cycles in one go?
Thanks

Rick


Re: ATMEL EEPROM endurance?

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It means the chip is _guaranteed_ to do 100k cycles
and will become flakey some time after that. How
long after is anyone's guess. If that is important to
you check the Atmel site they will probably have
statistical data on longevity.

Mike Harding


Re: ATMEL EEPROM endurance?
On Wed, 15 Oct 2003 12:40:34 +1000, Mike Harding

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Sorry missed a bit:
afaik the chip doesn't care about the relative timing of
writes so you could do 1 a year for 100,000 years (hmmm)
or 10,000 a day for 10 days.

Q:
If you write to one single location 100k times is all
memory subject to failure after that or just the one
location/block?

Mike Harding


Re: ATMEL EEPROM endurance?
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Each bit of eeprom is a stand alone memory cell. So you can change the
state of each bit from 0 to 1 (or 1 to 0), 100,000 times. After that you
might find the bit gets stuck at zero and you can't erase it back to 1.
--
Tim Mitchell

Re: ATMEL EEPROM endurance?


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I wwas wondering about this recently. I just want to store a couple of
parameters every time a control is altered. If the write operation
fails, I'll use the next locations. Haven't tried it yet, though.

Leon
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Re: ATMEL EEPROM endurance?
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That only works if the next location is not used by another variable.

Rene
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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Re: ATMEL EEPROM endurance?
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If the write operation fails with a specific byte, then , make shift
for
all parameters block , providing there is enough free space in EEPROM
( this is usually the case).The remaining thing to do is to use
special location in EEPROM which points to the parameters block and
update this
pointer if shift of the parameters took place.

Yossi

Re: ATMEL EEPROM endurance?

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What if *that* location breaks down too?
I think you can better use some sort of smart search algo on startup
(start from the end, searching for the first used block) than a pointer.

Wumpus


Re: ATMEL EEPROM endurance?

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If you continue along this line of tought, you'll end at wear-leveling
algorithms used in Flash file systems. Not a bad idea at all.

Tauno Voipio
tauno voipio @ iki fi



Re: ATMEL EEPROM endurance?
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Nice idea.  However, there's no guarantee that failure means the write
operation fails immediately.  It may just fail to store enough charge to
last more than a day, a month or a year.

Also the Jedec standard says that if < 5% of parts fail a test at, say
100,000 cycles, then that part has passed the test for 100,000 cycles.  Some
manufacturers put more stringent requirements on their parts of their own
volition.  A good intro is
http://www.microchip.com/download/appnote/eeproms/00601.pdf

Cheers,
Alf Katz

snipped-for-privacy@remove.the.obvious.ieee.org




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Re: ATMEL EEPROM endurance?
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 From my reading, the failure is caused by electrons tunnelling
only part-way through the insulator around the isolated gate, and
being trapped there where they can't be erased they make the cell
read as zero (cannot erase back to one). The number of cycles can
be a bit misleading - in chips where you control the timing yourself
the failure can be caused by a single very long write cycle, of
the required total duration. Something to think about if you're
writing programming software, because a failure which leaves the
programmming voltage applied will fail that cell really quickly.

Clifford.


Re: ATMEL EEPROM endurance?

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Use an FRAM chip from Ramtron. 10^10 read/writes (read is actualy a
read/rewrite). Cycle time 100 ns.

We save data 3 seconds after last user interaction. Never wears out.

Regards,
Arie de Muynck





Re: ATMEL EEPROM endurance?
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Amazing stuff isn't it?  Core memory makes a comeback.  ;-D  At least
some PIC's have a warning about rewriting a location many times
(approaching 1,000,000) can corrupt other locations.  Therfore they have
suggest refreshing everything once in a while.

michael


Re: ATMEL EEPROM endurance?

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Not quite - the basic physical mechanism is different.

Core is based on hysteresis of square-loop ferromagnetic material (often
called a permanent magnet), and the Ramtron FRAMs are based on the
ferroelectric effect (see Ramtron web pages for an explanation).

Been there - used them (both core and FRAM).

Tauno Voipio
tauno voipio @ iki fi



Re: ATMEL EEPROM endurance?
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Good spoken.  However, a) how do you find out if the write operation
has failed?  b) when reading the data, how do you find out which
locations contain the good copy?

Re: ATMEL EEPROM endurance?
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It means that the eeprom is toast after 100 000 write/erase cycles.

Wumpus


Re: ATMEL EEPROM endurance?
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Not exactly.  It means that you should assume that it's toast after
100,000 cycles.  ;-)  Actually, in normal use you'll get many more
cycles than that.  The spec assumes worst case conditions for the EEPROM
when writes are occuring.  This would normally be at the max temp
rating.  Fortunately, most applications probably wouldn't need to be
doing writes at 125C.  ;-)

michael


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