ATE Test: how many push fingers?

Isn't that the radius of the pushing surface of the 'finger', so it's not a flat end, but a slight curve? the diameter of the 'finger' should be a lot less. 3.2" diameter sounds more like an elephants foot that a finger.

The document says 10 always? I would say it depends on the number of nails, the size of the PCB and so on. The function is to avoid excessive bending.

ATE typically tests the board before depanelization. Some if not all of those fingers will press down on the panel in the waste area around the edge. Some will press at the point where four boards meet, typically covering a mounting hole at each corner, which is already partially waste space.

Hi,

- A 0.160in (4.1 mm) diameter keep out area free of components should be made available in a grid-like pattern every 1.50 in to 2.00 in (3.8 mm to 5.1 mm), across the entire surface of the board. A rule of thumb is to provide one pusher for every 10 probes.

- Additional sites may be required in areas of high probe density such as around ball grid arrays (BGAs) or near connectors. In certain cases, it is acceptable to push directly on the BGA or connector.

-The height of Push Fingers should be within 0.15

If I understand correctly, the keep out area of the push finger should be 4.1 mm diameter.

I don't quite understand "The height of Push Fingers should be within

thanks, Enrico

Enrico schrieb:

...so this is not *1.6in radius*, but *0.16in diameter*. That's correctly 4.1mm, which seems pretty reasonable.

Error on unit conversion: 1.5in to 2.0in is 3.8 to 5.1 *cm*, not mm. This again appears reasonable.

So it's not always 10 pushers, but one pusher for every 10 contact needles - to handle the forces of their springs.

Logical, isn't it? If you have an area with very many contact needles, you will apply much force locally, bending the board - unless you also provide more pushers at the component side.

This sounds like the height tolerance (between the many fingers).

The person who gave you that specification should be able to explain you what they really want. Why don't you simply ask?

Tilmann

Since the guide mentions "keep out area free of components", I assume it means that this is a circuit card assembly test, not a bare PWB test. Some boards are assembled while still panelized, but many are not (particularly if PWB fab is contracted out by the assembler).

Andy