Arm7 or Freescale Coldfire?

[Freescale PPC debug interface]

Does PPC JTAG support real "background" memory access, or is it like the ARM debugging where you need an interrupt routine?

If the latter, that's not "good enough an interface" IMNSHO.

Oliver

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Oliver Betz, Muenchen (oliverbetz.de)
Reply to
Oliver Betz
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Not true anymore. Background memory access while the core is running (and infact entirely separate from the core) is supported by SOCs with an ARM CoreSight debug interface as long as the SOC is designed in the correct way.

-p

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 "What goes up must come down, ask any system administrator"
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Reply to
Paul Gotch

Oliver,

I don't know. Since the interface is secret, I am not using it, all my debug tools rely on infortmation the manufacturer is willing to provide - BTW, I am doing quite well, although it would be nice to use all the capabilities since I do use JTAG anyway for boundary scan and initial flash programming.

Dimiter

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Oliver Betz wrote:

Reply to
Didi
[real "background" memory access on ARM]

thanks for this interesting information! Is it enough to look for "CoreSight" in the specs to see whether it's supported, or are there other names for it?

Do you know which derivatives, especially smaller (cheap) ones (e.g. up to 128K Flash and 100 pins) support it?

Oliver

--
Oliver Betz, Muenchen (oliverbetz.de)
Reply to
Oliver Betz

You've probably now seen

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Funny how LOTS of devices announce around ESC time :)

-jg

Reply to
Jim Granville

In what way more efficient? I can imagine it assembles faster but it sounds unlikely that it can produce more efficient code than a good C compiler - writing assembler is a lot more tedius than C, and compilers are really good at brain damaging tasks like register allocation, parameter passing, data layout etc.

There has been a lot of research into universal assemblers, and the result is often something similar to C (C-- for example, others consider C an assembly language), or a high level assembler with some macro facilities to get loops, if and switch statements, structures etc.

Who does the data layout and register allocation? Do you have a description of VPA and what it looks like?

PPC has some pretty good implementations as they were targeting desktops, and they are indeed high-end (and as a result high-power). However there is no reason to believe other architectures can't produce high-end implementations with similar performance. Many embedded architectures already have fast superscalar implementations or are working on them (eg MIPS, ARM, SH). It is now possible to do 1GHz with less than 1 Watt, so you'll see more high-end implementations.

Wilco

Reply to
Wilco Dijkstra

Okay, I'll bite. What is "fast loop mode"? I know what loop mode, introduced on the 68010, is.

~Dave~

Reply to
Dave

Yes. If you do just an instruction trace on a logic analyzer, the processor appears to have entered a black hole for some period of time, then it "escapes" and resumes normal execution. Makes for an interesting trace for a junior engineer to explain. ;-)

~Dave~

Reply to
Dave

I'll take your word for it - I haven't used any PPC chips other than the MPC5xx line. I do see, however, that the MPC55xx line have dropped the BDM, and have JTAG only for boundary scan. For debugging, they use a Nexus interface (which is also available on the MPC5xx, but I haven't tried it). The Nexus interface seems to be able to provide real-time tracing, like the BDM, but runs faster and has more pins (the old BDM is too limited to handle real-time tracing at higher speeds, with features such as pipelining and speculative execution). Again, this is a dedicated debugging interface rather than a simple serial backdoor such as JTAG.

As to how well it is documented, I don't know - I've never had occasion to look at the details.

Reply to
David Brown

It's a mode when you have a single-word instruction followed by a DBcc instruction in a tight loop, such as generated by the code: unsigned short int n = 1000; while (n--) { *p++ = *q++; }

Of course, it could well be that the 68010 has this mode - the CPU32 manual isn't very clear on which features are new compared to the 68000, or compared to the 68020 (the 68010 was not much used, was it?)

According to the CPU32 manual (I've got it open at the moment anyway), the extra features of the CPU32 include low-power modes, and table lookup and interpolate instructions. Missing instructions include the bit-field instructions, compare-and-set, coprocessor control, and BCD instructions.

Reply to
David Brown

ABCD and SBCD are indicated as being 68K family instructions.

Reply to
Everett M. Greene

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