8051 architecture question

google for "8051 memory", lots of info

Yes, it can be easies to consider a vanilla romless device. There, PSEN enables CODE memory, and WRN/RDN control the XRAM, so there is a total of 128K, as 64K code and 64K XDATA. That is also why there are distinct MOVC and MOVX opcodes.

In modern devices, mostly CODE is on-chip and XDATA can be mapped onto on chip XRAM, and also on chip EEPROM. The AT89C51ED2 is a good example of this.

If

They sound variant/vendor dependant, and are not C51 core specific.

-jg

Completely separate. This it what is known as a Harvard architecture where code and data spaces are kept quite separate. In the 8051 you can have up to 64K of each.

Ian

Fully agree. Just want to add that one can map the mcu signals in a way that both code and external memory are the same. Many development kits do this by default to allow the user to "upload" code into the external data memory of which a certain part will appear as the code memory. Coding wise this leads to a point where movc and movx will access the same memory location. However this breaks the Harvard paradigm (ofcourse).

just my 2c, Matthias

The answer is "it can be". You can either split the data and address spaces, or join them. The processor becomes slightly harder to program in its split configuration, for example, it is more difficult to load constants from the code space if, for example, you place the rom there and need to access that.

Most of the places I used (ok, all of them) used the 8051 as a unified address architecture.

There are 3 memory spaces (without tricks and such)

The reserved memory area does nothing, it is extra space to add things in the future. scratchpad memory is a programming term not an 8051 memory space. look at

Assuming a basic 8051 (not a '52, no internal flash or whatever):

-- There is 64Kbyte of program space, and 64Kbyte of data space. The program space is read-only and enabled by the CPU's #PSEN line; the data space is read-write and enabled by the CPU's #RD and #WR lines.

You can hold read-only constant data in program space, but you are limited as to the instructions and/or addressing modes by which that can be accessed. The assembler instructions used determine which space to deal with: MOVX refers to data space, and MOVC refers to program space.

There is, of course, nothing to stop you hardware mapping the same physical memory (or a subset of it) so that it appears in both data (MOVX) and code (MOVC) space.

On the plain 8051, you don't get the full 256 bytes internal RAM: you get 128 RAM + 128 SFRs. It is only on the '52 architecture that there is a full 256 bytes of internal RAM: the upper

Richard [in PE12]

On the plain 8051, you don't get the full 256 bytes internal RAM: you get 128 RAM + 128 SFRs. It is only on the '52 architecture that there is a full 256 bytes of internal RAM: the upper

Richard [in PE12]

Sorry for double-post. Bloody Outlook Express.

Richard [in PE12]

Get Intel's original MSC-51 family user manual. That's got the most complete description I've seen. Most of the subsequent manufacturers omit and/or gloss over most of the basic info and show you the differences and additions.

Google for it, and if you can't find it, come back and I'll snicker at you.

Best regards, Spehro Pefhany

Yes, I have an old, dog eared Intel book of the 8051. I went to the Intel site, and lo, and behold, their users manual for the 8051 is that exact same manual as I got 15 years ago. It even looks like a scan.

Yup. It's got hyperlinks, but they are on top of the scan. Mine is dog-eared, but I don't dare touch it much these days as the paper they used was pretty crummy. The MCS-48 section is somewhat depleted.