noisy logic

What is "a lot of noise"? Is this output changing state? Perhaps you're just seeing the noise in the logic's power supply (which will appear at each output, too).

Look at the noise on the logic's power pin with respect to whatever return you're using when measuring the output noise. I'll bet that the magnitudes will be very similar.

Assuming that this is true, you can add local capacitor decoupling across the logic chips if you don't like seeing this noise, but be aware that you still may see noise because of your breadboard's high impedance returns (grounds).

Bob

You can get very short glitches on the output of combinatorial logic if the same input signal propagates via two or more paths through the logic with slightly different propagation delays.

Say your logic was Y = A AND NOT(A). Y should always be 0; but you get a glitch on the rising edge of A because of the delay through the NOT gate. The AND gate very briefly sees both inputs high.

Thats probably it.

My equations are B or (~A and B) and similar ones. So I guess the extra delay in computing the sub equation causes the problems ;/ (B is the PWM signal)

Is there any fixes?

ic.

or

ic.

or

Synchronous logic can be organised so that combinational outputs have had a chance to settle down before they get clocked through to a latched output.

With pure combinational logic you can sometimes delay one input to cover the uncertainty on one edge, at the cost of a larger spike on the other edge, which you can then mask with an extra delayed input, but this is rarely either necessary or justifiable.

-- Bill Sloman, Nijmegen

if you have only two inputs such an arrangement is pointless. use either the and gate or the or gate as necessary.

Bye. Jasen