Puzzling circuit in EDN design ideas (NE555 voltage to frequency converter)

Can somebody help me understand the circuit in

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an NE555 based voltage to frequency converter. I tried simulating the circuit in LTSpice but couldn't get the NE555 to work.

The article says that first the capacitor will be charging with an applied negative input voltage. So far so good. When the output reaches a certain voltage the discharge transistor Q1 will turn on and reduce the output voltage.

This is what I don't get. If the voltage is decreasing on the cap after Q1 is turned on, we have now 3 currents at the negative input junction of the OpAmp.

1) Q1 current going upside down 2) Input voltage current going from right to left through the resistors P1,R1 (0 to a negative voltage) 3) Cap discharge current going from left to right (The only way I can think of if the output voltage is decreasing).

So now we have at one junction, 3 positive currents going away from the junction, which by KCL is impossible.

So what am I missing ??

Thank you.

Reply to
ShamShoon
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I don't think it works, either.

The voltage on pin 2 of the opamp is a virtual ground, very=20 nearly zero volts. The discharge transistor can draw no=20 current from that node.

An editor?

This line is completely wrong: "As the voltage on C1 reaches two-thirds of VCC, the 555=92s=20 internal discharge transistor opens, and the voltage on C1=20 returns to one-third the voltage of VCC, the lower=20 comparator threshold." Q1 turns on after the threshold=20 voltage exceeds 2/3rds of the supply voltage, not turns off.

But it doesn't matter, since there is no source of positive=20 current into the opamp inverting input, top run the miller=20 capacitor negatively. You would need a positive current=20 source switched on and off by Q1 (on when Q1 pulled low) to=20 make this work. I think they lost a PNP transistor in=20 translation.

--=20 Regards,

John Popelish

Reply to
John Popelish

On Mar 2, 2:49 pm, John Popelish wrote: [snip]

[snip]

Thanks John. Now I got some of my sanity back. I think the editors should have done some verification before including it.

Reply to
M. Hamed

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Most of the EDN submitted circuits are crap. They're just filler, to keep the "editorial" content up enough so they can ship ads at the cheap "magazine" postal rate. They're all journalism types; what would they know about electronics?

John

Reply to
John Larkin

There seems to be an error in the schematic posted. Pin 7 should probably be connected to the trigger/threshold node, not to the input of the opamp. I'm guessing that they want to discharge the integrator cap when it gets to 2/3 of Vcc.

Regards, Bob Monsen

Reply to
Bob Monsen

The editors did their job. I didn't spot a single misspelled word.

Bob

Reply to
BobW

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