I've having some difficulties using a GAL on a 25 year old PCB - I have the correct JEDEC file and my programmer will handle the GAL okay (a GAL16V8D-25QPN) but the board won't work with the newly programmed GAL.
Why is this likely to be?
Something to do with the type of GAL or perhaps even the speed? (although I would have though that a -25 would be fine for a 25 year old PCB).
No - the original chip was an 82S153 PLD, it's just that someone converted the contents of that to JEDEC format to work with a modern GAL (82S153's are hard to find and expensive). It worked for him, just can't figure out why it won't work for me.
So perhaps I should buy and try a faster GAL? -15 perhaps? -10? -7?
Ah, pals and gals maybe I'll still get a chance to play with those. I would say you are most likely already way too fast, 250-300ns RAMs in those days, 82S153 probably had propagation delay of at least 40ns come to think of it it is not even PLD it is a PROM hence even larger propagation delay can be expected. A quick glance on goole, I don't see anythink with specs ( so many useless hits these days $#*%^& ) It is not in the "CMOS cook Book" must be in "TTL Cook Book" anybody have it handy? Of the top of my head I don't even think it has an enable signal which you could ..... The old slow part may be bridging the time the inputs stop being valid and the outputs are read (since I don't believe the part has output enable), the only way would be to buffer the outputs or use a device that could delay the outputs internaly.
Why it worked for the other person (with same circuit, same speed and type GAL ) can't say. Maybe you can get a bit slower GAL and get lucky.
"matt" schreef in bericht news: snipped-for-privacy@news.freeserve.net...
Maybe. But I'd be mistrust the conversion in the first place. Do you have the JEDEC of the original 82S153? If memory serves, AMAZE can convert the JEDEC back to logic equations so you can see what it is supposed to do. Once you know that you can edit the source for a GAL and get the right JEDEC for it.
days, 82S153 probably had propagation delay of at least 40ns
propagation delay can be expected. A quick glance on goole, I don't
in the "CMOS cook Book" must be in "TTL Cook Book" anybody have it handy?
could .....
outputs are read (since I don't believe the part has output enable),
the outputs internaly.
) can't say. Maybe you can get a bit slower GAL and get lucky.
Is it really everything identical as the other person is doing? Even metal plate (grounded or not hmm) under the circuit could possibly make a difference. Do you have the schematic? Converting to new pals, sounds like something I read a while ago with regard to fixing an old video game. Sounds like you are programming the PAL yourself so you must be able to make a circuit board that would plug in place of the PAL and contain the new GAL
74??374 or 74??574 for the outputs and hex inverter to delay some clock signal . I maybe wrong and there is an enable input which you'd run through the inverters and to the clock of the ...... well this is already going in the wrong direction hehe. Maybe it is more trouble than it is worth. I could be done, but very difficult without deriving the timing from the board.
The board is okay as it works with the original 82S153 (which I can't dump and don't have a replacement for - I'm testing the GAL on this board but it will be going on another board (same type) as that one has a bad 82S153).
I'm guessing that that guy who created the JEDEC file (a few years ago now) used a slower GAL.
Yup, except maybe he used a slower GAL? I don't know, just guessing.
difference.
No, seems to be except the same I'm afraid.
a while ago with regard to fixing an old video game.
Yes, the schematic can be found here:
However, it's a 12MByte file as it's the complete manual - the schems are towards the end of the PDF, you'll need to look at those for the Memory Board. The device is question is the PLS at location U10
BTW, the quality of the schems is poor in places, but just about readable.
It's a GAL. :)
and contain the new GAL 74??374 or 74??574 for the outputs and hex inverter to delay some clock signal .
inverters and to the clock of the ...... well this is already going in the wrong direction hehe.
Yes, maybe. Depends if it would work or not, and not sure if I could do it without exact instruations on what to connect to what.
"matt" schreef in bericht news: snipped-for-privacy@news.freeserve.net...
Sure, but JEDECs differ widely for different components. They often even differ for the same component type but other manufacturer.
As for the speed itself I shouldn't expect problems. According to the Philips datasheet the standard N82S153 is rated for 40ns, the N82S153A is rated for 30ns. So your 25ns GAL may be too fast rather then too slow. But in that case I consider it either a poor design or the use of some special trick. Which will not help you, I'm afraid.
BTW It worked for someone else. Do you mean same board, same 82S143 content and same object GAL? (So same type and brand?) Any idea what the GAL is supposed to do? Any problem posting the JEDEC(s) you have? (Part of) the schematic?
Same board, yup (well, same design, same manufacturer, etc).
Same GAL type: GAL16V8D - not sure what speed or brand he used though as he's not replying to his emails.
I'll quote from the chap who came up with the JEDEC:
"All ROM and RAM on this Memory Board is initially decoded by the
82s153 FPLA at location U10. The FPLA enables address decoders based on the upper 3 address bits of the address bus. Additionally, the FPLA prevents ROM and RAM access during certain system processes including: refresh cycles, active resets, I/O requests and a architecture specific signal called /BUZOFF. The FPLA contains 5 address inputs and
7 status line inputs. Outputs of the FPLA are 4 decoder enable lines and 1 transceiver direction select line. The enable line for ROMs X1 through X4 (74LS139 at U8, pin 1) is selected on addresses x0000-x3fff ( !a15, !a14). The 4 ROMs are then selected off of a13 and a 12 by the lower half of the 139 decoder at U8. All the other selects work similarly. The second half of U8 (pin 15, enable) selects ROMs X5-X8 (a15, !a14), the lower half of U9 (pin 1, enable) selects the ROMs at X9 and X10 (a15, a14, !a13)and the upper half of U9 (pin 15 enable) selects one of the 4 RAMs (a15, a14, a13) based on address lines a11 and a12).
The FPLA also selects the direction of the 74ls245 transceiver at U17. On a write, pin 1 of U17 is held high to allow data to flow from the processor data bus to the RAM/ROM board data bus, on a read the line is held low and the data flows in the opposite direction. Most of the additional circuitry on the ROM board deals with selecting the RAM at X21 for high score and setup information. The three 74ls244s at U16, U15 and U 11 are all used as line drivers with all of their select lines tied low permanently.
The original FPLA used is a Signetics 82s153, which is now obsolete, a modern replacement is a Signetics pls153, however I have not been able to get a good copy of one so I had to write a replacement using a PLD (GAL16V8D)."
Here it is from the guy's site:
formatting link
I don't know how to extract a page or two from a PDF, but the whole manual (12 MBytes! with schems at the end) can be found in this file:
formatting link
you'll need to look at the for the 'Memory Board'. The device in question is the PLS at location U10
BTW, the quality of the schems is poor in places, but just about readable.
Can't dump it? Can't you plug it into a breadboard, put a counter on the inputs, and see what you get at the outputs?
Then you would at least have a truth table, unless it's got some kind of embedded state machine or something. It'd also help to know if the outputs are latched or anything. Is there a data sheet anywhere on the 82S153?
LOL, rotorooter? Let us know when you are fixing at least burger time hehe.
The most suspicious signal is the last (bottom) output controlling the U17 as someone suggested, resistor may work. Two transistor driver ( optionally with RC on input ) or run all outputs through 74L244 (L only, if it exists) although that only adds about 12ns, 'L' would probably be about 20ns. I'd try the following, adding R1( and C1 only if needed, start in center position and reduce.
Or if using R1 C1 drop the second transistor with its resistor , put 1-1.5 K resistors between collector and +5 and emitter and GND and take the signal from the emitter. However, this may not be a good idea for a digital circuit (slow rise time).
Now fire up that slow comp and it is time for a little Major Havoc, hehe.
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