That would be nice, if the coarse DAC would have ideal voltage steps.
While you could use four serial (UART) ports to generate 3 bit PWM each and after filtering, sum the currents with 512:64:8:1 ratios, I very much doubt that you would get a monotonic 12 bit response, not at least without tweaking those resistors on a case by case basis.
I have seen that for A/D and D/A converters since the late 1970s. I suspect the idea came about from multispeed synchro systems, where=20 two synchros geared say 36 to 1 were both used to transmit position=20 information. Google it up.
12bit? Easy. Seems like Steve will need a lot of more bits. The trick is to PWM some stable reference voltage, not just take the 3.3V that comes out the uC (could be noisy).
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Regards, Joerg
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What I'll never understand is why this stuff is not taught at universities. I've often seen situation where a freaking expensive DAC had been used and then I replaced it with a cheapo dual, and once a guy said "Now that's cheating!" after he lost a (beer) bet that it could be done under five bucks :-)
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If you want to use a 16-bit D/A-card you can scale down the output to
100uV/step and filter it, so you get a smooth ramp. There will be a delay of
4s on the ramp an when it stops the last 250uV will settle assymptotically. The opamp is a precision part and is stablr with any capacitive load. It can source or sink up to 20mA and can be supplied by the reference Voltage, if your 2nd channel on the D/A.card can output that much. otherwise use a separate supply and take only the 10V reference voltage from that channel. If you have the option of unipolar output, no reference voltage is needed. The lowest reachable voltage with 100k load is +10mV, with 1k +600mV, if that is too much you also will need a negative supply for the opamp. If you need more output current, you can add a buffer like LT1010 (inside the fb-loop) Vrefo+10V | o----------------. | | .-. | | | | | |20k |
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