Very low frequency 100 microvolt/sec triangle ramp with adjustable limits and slope

They do but only if they are really tucked away and cut off from the environment (moisture, pollution and so on). The datasheets usually state several tera-ohms for the more expensive caps:

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I found that in reality they aren't quite as great. Analog slopes longer than 10 minutes are usually a royal pain.

Yes, you can do a lot with guard rings and so on. But again, you'd almost have to encapsulate the whole thing.

Naturally I am all for analog because that's my bread and butter. But to be honest, I would PWM this one.

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Joerg
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Reply to
Steve

That could work. Use several of the 16-bit outputs and sum them into a node. Set the resistor to ground so that full scale covers 4.8V. You can add in an offset to get the -10V to 2V for even better granularity. That, plus a nice RC lowpass and you could be home :-)

Just make sure the offset comes from the card, like from another DAC, so you don't back-feed into the card when someone trips over the computer's power cable.

[...]
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Joerg

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Please bottom post (or inline post where appropriate) in order to keep
the thread chronologically coherent. 

Thanks. :-)

I've already posted a digital scheme which will allow you to accomplish
what you said  you wanted  to do, but without the constraints you've
introduced which the "less expensive" DAC cards will place on you.

can you tell us what, exactly, you want to do and how much money you've
got to be able to do it with, please?

JF
Reply to
John Fields

Apparently these devices use R/2R type DACs.

While in principle a high speed low resolution DAC could be used as a slow speed high resolution DAC by oversampling, the linearity errors could be a problem with such slow ramps.

While an ideal 12 bit converter would generate a clean step from say

7FF.00 to 800.00, the actual analog step could be 7FF.ff to 800.00 and the device would still considered monotonic :-).

At least a quite large (several LSB) dither noise amplitude in the digital domain needs to be added, to get rid of the worst linearity errors. Some RC filtering on the analog side will then remove the dither noise.

On delta/sigma etc. type converters the fluctuation of the clock would alter the output value, thus an oscillator with low phase noise is required and the oscillator should also be free of microphonics, unless the RC filter cut-off would be below 1 Hz, however, such filters would either have a very high output impedance or would require a huge non-electrolytic capacitor.

Thus, high quality timing is requiring, so that the analog RC filter would only have to remove oversampling noise, thus operating at a high (100 Hz - 10 kHz) cut-off frequency.

Reply to
Paul Keinanen

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Reply to
MooseFET

t

It depends on whether you need a perfect ramp or only a monotonic rise that is good over modest spans.

The Silabs ones appear to have a step size that is always within about

1/4 LSB of what it should be.

The dither can be done at the update frequency of the DAC and it works quite well. I have done it. The low pass filter needed to get a good signal in the 0-100Hz band is not all that hard to do. The dither doesn't need to be random. My code tends to create chaos for the points that are not rational values. For others it makes a fast cycle of 3 points.

Doing a cycle of 3 bits on a 12 bit converter means that the timing issue starts off 60dB+ down from the full scale. This means that an oscillator with jitter in the important band that is 5 digits down will do as well as 24bits.

The non-electrolytic capacitors in the filter have to be large but not huge.

!\ ----/\/\----+---! >-----------------------+---+-- Output ! !/ ! ! Clarge=3D=3D=3D ---/\/\---+---/\/\--- \ ! ! ! / ! /-!- \ -------+----< ! ! \+!----------------+ ! =3D=3D=3D Huge but leaky ! GND

You don't get 2 poles worth of noise supression but the leakage in the huge capacitor doesn't create an offset.

Reply to
MooseFET

Easy enough. Use an op amp integrator, and variable voltage source (a potentiometer) feeding a few-megohms input resistor as a current source. 10 uF capacitor, 20 Mohm resistor, op amp (I did one with two-day ramp time with old CA3140) and 100 mV applied from the potentiometer yields a ramp rate of 0.5 mV/second or 1.8 V/hour. Using +/- 15V power, you get your 15 hours before the op amp runs out of range.

Scaling and offsetting the ramp with a second op amp completes the project.

Reply to
whit3rd

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Always a bridesmaid, never a bride...

JF
Reply to
John Fields

--
The worm turns?

Refreshing...

JF
Reply to
John Fields

This will be scanning voltage for electrochemical compound research for battery cycling. Slow scan needed because of slow diffusion in the materials. University research, so money is an issue. Even hundreds of dollars cost difference can be an issue. Looking for in-lab built device(s) instead of spending thousands for a commercial instrument. 12 bit DAC interface cards are $150, 16 bit are $400.

Reply to
Steve

I'd get an EE student to design, build and test it. Lots of them would love that job, they aren't expensive, they have to learn the ropes anyhow and when they can stuck they can ask here :-)

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Reply to
Joerg

How about a gear motor and a 10 turn pot?

Reply to
MooseFET

with

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output

Yep. Even if you used high frequency dither to get a smoother average=20 slope out of the DAC.

Reply to
JosephKK

with

voltage

=A0It

output

but

=A0Since

Yes. More interestingly, the dither pattern can include a low value=20 linear slope component as well. The result is sometimes called noise=20 shaping.

Reply to
JosephKK

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There are a couple of interesting publications in the area. I dug them out a few years ago for a comment I published in the Review of Scientific Instruments

'Comment on "Noise averaging and measurement resolution" [Rev. Sci. Instrum. 70, 2038=962040 (1999)]', Rev. Sci. Instrum. 70, 4734 (1999); by A W Sloman

The original paper made some claims about essentially square wave dither; triangular dither is better, but not necessarily the best, or the easiest to generate

The abstract says

"The paper presents a superficial analysis, based on computer simulation, of a subject which has already been discussed at some length and for which analytic results have been presented. The authors appears to use "uniform dither" where several authors recommend "triangular dither" which gives 50% more quantization noise, but makes the quantization noise independent of signal level. The author also fails to mention the possibility of using "subtractive dither" which is technically difficult, but justifiable in expensive systems."

Amongst the classic papers in the area is one that talks about a "dying fall" in an early digital recording made for "The Who". My basic soruce was John Watkinson's "The Art of Digital Audio" ISBN-10:

0240515870 ISBN-13: 978-0240515878.

-- Bill Sloman, Nijmegen

Reply to
Bill Sloman

Who says you can only use one DAC? Use one for coarse and another for vernier. Oh, now I've dropped the bag'o tricks and spilled it out :-)

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Reply to
Joerg

rote: [.. dither on DAC ...]

od

What I do is keep track of the LSBs below the ones that could be sent the the DAC. These get added into the next value before preparing it to go to the DAC. This pushes the noise up towards the Nyquist.

The "dither" is a simple -1,0,+1 cycle that is scaled to be just a little under 3 x LSB. It forces there to be some bits going into the "lost bits" logic even if the number happens to have all zeros below the point where it gets cut off for the DAC.

=A0 =A0 =A0 =A0! =A0 !

=A0\

=A0 =A0 =A0 =A0 =A0 =A0/

=A0 =A0 =A0 =A0 =A0 \

=A0 =A0 =A0!

-------+

=A0 =A0 =A0 =A0 =A0 =A0 !

=A0 =A0 =A0 =A0 =A0 =A0=3D=3D=3D Huge but leaky

=A0 =A0 =A0 =A0 =A0 =A0 !

=A0 =A0 =A0 =A0 =A0 =A0GND

Reply to
MooseFET

--
Ahhh! In-lab built!

Since you've got in-house test and assembly talent, I'll post a
schematic for you in a day or so that should get you what you need for a
few hundred dollars, probably including PCB fab if you're careful. ;)

JF
Reply to
John Fields

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put

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Ahh you'll never see this reply, but Thanks Joerg, that sound like a nice trick to tuck away.

George H.

Reply to
George Herold

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