Transmission line-like resonances at ~30MHz

Thanks for the ideas, Fred and Joerg.

"Fred Bartoli" wrote in message news:420a90d1$0$29252$ snipped-for-privacy@news.free.fr...

Hmm... so... thinking about this a little... I was thinking a bunch of little lumped capacitors along a transmission line wouldn't electricially shorten it, but would rather just add a regular RC-like roll-off to the response. From what you and Joerg are saying, it sounds as though all the little caps electrically shorten the line... period.

They're supposedly 50 ohm lines, although I haven't verified this and personally suspect they might be somewhat lower. The traces are 12 mils wide and... if I were at home I could get you the trace capacitance from this, but unfortunately I'm not so I can't.

The are numerous (~50) PN diodes hanging off of them (Agilent HSMP-4820); the traces carry RF and the PN diodes are used to switches to route the RF to one of numerous outputs. The 30/90/150/etc. MHz dips occur when none of the diodes are turned on (the dips shift around when the diodes ARE on, which is what I'd expect).

The HSMP-4820 is spec'd as being 0.75pF typically... hmm... ok... it sure does sound as though this must be the problem. Grrr...

Thanks again,

---Joel

---Joel

Looking at a Smith Chart, it's clear to me now that small lumped capacitances along a transmission line will just make the line look electrically longer than it physically is. Hmmmph. I have a few ideas about how to fix the problem; namely by terminating the line and then adding amplifiers.

I shudder to think what the frequency response of some of the digital circuitry I've designed over the years has been... I wouldn't have guessed that 12" traces could already exhibit significant distributed behavior at

---Joel

A transmission line that's periodically (or worse, non-periodically) loaded by capacitors (or worse, lossy capacitors, like a CMOS input) looks lower in impedance and slower in prop delay than the unloaded trace. If there are lots of small loads spaced close, you can just pretend the C per unit length has gone up, and recalc the trace impedance. If the loads are lumpier compared to the signal risetime, you enter reflection hell. Your skinny traces probably have much lower native c/length than the loading, so the line will be a lot different than the raw trace. Heavily loaded lines like this tend to be lossy, which is sometimes a good thing. Risetimes tend to go to hell.

Extreme cases, like backplanes, can be awful.

I just did a board that has 14 schottky diodes spaced uniformly along a 4" long trace, with the trace widths fudged down to give a 50 ohm line when loaded by diode capacitance. Each diode has the option to inject a 200 ps pulse into the line. Pretty much works, although some of the waveforms along the line are kinda strange... seeems to be a bit of bouncing going on.

John

Hello Joel,

Lots of capacitive loads hooked up to them? An innocent CMOS input can add 10pF easily. Each.

If these are clock distribution lines you need to terminated them with their respective Z, as calculated from trace width, layer respectively prepreg thickness and the dielectric constant of the material (probably FR4). Hoping there is a solid ground plane underneath, that is.

Regards, Joerg

"Joel Kolstad" a écrit dans le message de news: snipped-for-privacy@comcast.com...

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Additional capacitive loading along the trace?

What is your trace capacitance per unit lenght? At 50p/m and 0.3m length you need 360p additional "distributed" capacitance to get there.

Hello Joel,

They can make resonant circuits out of it.

The capacitance will be higher, with SMT lands, traces and all things considered. Maybe you could post a schematic so people can toss some ideas as to what could be done. You might want to try some termination at the end but it is unlikely to give enough of an improvement. You will also need a pretty stiff driver with this many diodes as a load. What resistance is in series with each diode?

Regards, Joerg

"Joel Kolstad" a écrit dans le message de news: snipped-for-privacy@comcast.com...

Yes, don't forget your small bit of line still has its inductance. At low frequency, (this is LF compared to your bit of line lenght) you'll have a bunch of L-C cells where the C isn't the one you think from just the line.

Not anymore : sqrt(L/(C+Cpar)) is lower due to Cpar

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Also don't forget the stubs that connects the diodes to the line.

For example you can build a slow line by just adding a truck load of stubs along the line, thus increasing its distributed capacitance without touching the inductance.

BTW, if you've calculated your line to be 50R or whatever, the additional parasitics will lower it, but I've already said that.

Hello Joel,

Termination is always a good idea. Then look at the load points. How much do these diodes draw from the line when turned on? Maybe a little transistor buffer for each could help.

They can work very well up to a GHz and more, provided they are nicely terminated and Z is the same along the whole trace. No sharp turns, no big loads along the way.

Regards, Joerg

I think FR-4 has mu_r = 4.7

The microstrip in question was on an outside layer, so as a rough estimate I used 4.7/2 as the effective relative permittivity.

---Joel

Programs like Txline and Appcad will compute effective dielectric constant. The classic 50-ohm microstrip on 0.062 FR4 has Eeff of about

John

Yes, I have a spreadsheet based on Howard Johnson's "...Black Magic" text, which also computes an effective permeability. Probably very similar formulas, since lo and behold it's about 3.4 for a 17 mil trace

Good day!

Just be careful about any simple formula. Most work over a small range of geometries. The classic "Motorola ecl" equation cruises clear through zero ohms and goes negative as the trace gets wider. I like Appcad and Txline, which are smarter. Both are free.

John

Thanks for the links. I could use some software to do this, as Johnson's formulas (actually from I. J. Bahl and Ramesh Garg, "Simple and accurate formulas for microstrip with finite strip thickness", Proc. IEEE, 65, 1977, pp. 1611-1612.) are not very simple, with various conditionals, functions of functions, and so forth. Once in a spreadsheet they are a cinch, but I don't want to have to type in the several foot long formulas for every geometry.

Good day!

The ultimate free tx line analyzer is ATLC, which will calculate the impedance of a cowbell-shaped line inside a star-shaped tube with mixed dielectrics. It's just an immense pain to use.

John

Hello John,

But Motorola did a good thing with their MECL design book. They made unsuspecting engineers aware that when digital stuff gets faster things ain't totally digital anymore.

Another really good source with formulas and all is Fairchild's 1977 ECL data book. I began using that one after my trusty old Motorola book literally fell apart. It didn't like California summers.

Regards, Joerg

after doing several of these, I hit on the following strategy.

Calculate the minimum and maximum impedences over all the loading conditions. Usually that means no loads and maximum loads. Then series terminate the drivers with the minimum impedance, and parallel terminate the end with the maximum impedance. Its not perfect, but one end or the other is usually close enough to damp out resonances.

Goggle

salphasic clock

for some interesting reading.

Mark

"It is estimated that the switching currents will peak at 1000 A unless tightly controlled clock skews are utilized to avoid simultaneous switching."

That's beyond interesting. That's terrifying.

John