tiny ARM processor

You can use GCC for AVRs too.

Well when they introduced them there was only the ARM7. They do CM3 now (and ~CM4 on another range of devices).

But yes in general they are relatively crappy cores with relatively better analog, compared to other suppliers.

At least some PCI card manufacturers put chips on the both sides of the PCB,

What is the cost of putting components on both sides of the VME PCB, What is the clearance requirement for the "solder" side components to the next VME card ?

If you can use low outline chips, you just need to put 16 ARMs on each side. Since you are talking about isolated circuits, what are the requirements between tracks (1-2 kV) ?

Parts on both sides of course need two passes through the pick-and-place. VME modules have front panels, and if you put parts on the back of a board, when you insert or remove a module the front panel of adjacent modules tend to scrape off those parts. It can be done with carefully placed thin parts, but we try not to. Bypass caps are the first things to go onto the back side, aligned so the solder fillets make sort of ramps to fend off the adjacent panel. Yuk.

I think 500 volt isolation would be plenty, so clearances are moderate. The i/o connector will be a d-sub, not a HV thing.

Looks like I can fit a channel into well under a square inch, even using a giant SOT223 fet and a big SMA-size TVS.

One good thing about the tiny AVR is the 1 pin debugging/loading over the reset pin. Unfortunately, not many other chip makers catch on to this features, not even Atmel (for other chips).

Yes, switching from an ARM to one of the many 8 or 16 bitters is actually a step in the direction of simplicity. But it is still a step. The initialization of an ARM is not so simple. Typically this is done in vendor provided startup code. If you need to modify that it can be a bit messy. AVR, MSP430 and the like are *much* simpler to deal with.

The one big sticking point is from switching vendor more than switching CPU line, that is the change in peripherals. Going from TI ARM CM0 to NXP CM0 is much more work than a switch of the CPU with the same vendor who uses the same peripherals. This can introduce errors that are hard to track down.

Saying they want to stick with ARMs is not nearly as important to an easy transition as sticking with the same peripherals.

That is an indication of something wrong with your design. The VME spec allows room for components on the "solder" side of the board. Partly this is because it dates from the days of through hole mounting and through hole parts have leads that protrude. If you can't mount an appropriate CPU part on the solder side of the board without it getting scraped off on insertion or withdrawal from the rack, you have a problem with your brackets or board warping.

Ask your mechanical designer to look into this.

That's starting to look like the stuff I design, barely room for parts and no room for routing. I highly suggest you give up the (x)SOP package you show for the MCU. Go with a leadless QFN. You save board space that is used for the leads and likely get a smaller body as well. If the board is this tight it will be important.

Hopefully your layout package can let you lay out this section once and copy it many times.

I can't imagine being limited to components one side only. They'd never fit. Our only restriction is BGAs and, of course, heavy stuff like aluminum caps.

Roger that. I try to stay away from anything with leads (other than stuff like SC70s) - waste of space. QFNs are great. I wish I could get opamp arrays in QFNs.

In this century, one would hope! John's done a lot of this sort of stuff, too.

You will want to check if you can do this with an M0 (or M0+) core, or if you want to have a M4 core. As Tim says, the smallest and cheapest devices are usually M0 - they are fine for many purposes, but an M4 core will be many times faster if you need to do calculations at speed.

The M4 is specifically designed to do DSP like calculations at near DSP efficiency. For example, it can approach 1 MAC/clock in doing FIR filters and correlations. But if the processor is doing nothing else, there are a lot of clock cycles with just 50 kSPS. So an M0 may do just fine. Heck, an MSP430 could likely do this job.

In my opinion, a small FPGA would be a good fit too, but you'd have to roll your own ADC/DACs. MicroSemi has mixed signal FPGAs, but I don't think they come in the really tiny packages. So an MCU is likely a better choice here.

We've done a bunch of projects with the LPC1768, which is an M3. In one case, we had floating channels, each with its own CPU. We ran a fairly extensive SPI/filter/PID loop at 100 KHz, and throttled the clock down to 50 MHz. A couple of hundred lines of code executed in about 5 microseconds. The ARMs are really fast. We shouldn't need a lot of CPU power to test and protect a mosfet.

No, because the channels are isolated.

JL: "Each fet is isolated, so we need a CPU per fet."

What part of that is hard to understand?

Altera's Max 10 has ADC. Can do a simple DAC with external resistor packs. John can put 32 soft CPUs in one FPGA. But the ADC and memories would have to be shared.

There can be 18 analog channels, but only 1 or 2 ADC converter.

He is using multiple CPUs because of high voltage isolation I believe. So for him, "one device to control them all" won't cut it unless the high voltage is just a matter of isolation from the user and not all the FETs from each other.

My point is that FPGAs are not much different from MCUs at the low end, except for memory, in particular flash. Even physically small MCUs can have a lot and the small FPGAs typically have little or no user accessible flash although an adequate amount of RAM. But some will initialize the RAM from the configuration Flash, so if there is enough RAM you can be good to go in a very small package.