Testing Idss of fet and not getting what I hoped for

John Larkin wrote in news: snipped-for-privacy@4ax.com:

what

mosfet.

4

It's

multistranded

vs

BANG.

You should get hold of the quarter shrinker folks. They dump

15,000 amps inside of a few ms. The 1/4 inch diameter 'wire' coil explodes. The quarter shrinks.

Don't try this at home...

Reply to
DecadentLinuxUserNumeroUno
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Winfield Hill wrote in news:q90j9g0b13 @drn.newsguy.com:

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Reply to
DecadentLinuxUserNumeroUno

John Larkin wrote in news: snipped-for-privacy@4ax.com:

I worked on a device we ended up not getting contracted to complete. But the intended use was as an EMP pulser to set off car bombs approaching the green zone in Iraq. They were going to be set up along the new jersey walled road that leads to the gate.

Reply to
DecadentLinuxUserNumeroUno

That's microseconds, high dI/dt with a 20kV storage bank. Bert Hickman hangs out here from time to time.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

I would be all for throwing an error for nets with the same name on different pages, or even the same page without an off-page connector. Nothing should be global by default.

Reply to
krw

Busses are labeled in a very different way, at least IME.

I've never seen them limited. IME, all names are global.

Reply to
krw

That works for FPGAs but it doesn't for most devices. Do you really use 64 individual signals for a 64b bus?

Reply to
krw

What matters to us is not minor conveniences, but getting boards right first pass. Explicit, visible offpages are safer than any other way to name nets. It's a lot easier to add jumpers than to cut inner layer traces and planes.

We do print and read the schematic net list to look for obvious mis-spellings and single-node nets and such. It's very rare for us to have a layout error that makes rev A unsellable; that hasn't happened in years.

We do pull out a few unused uP and FPGA pins to test points, which can be scoped or kluged to. My latest innovation is to not solder mask vias, which makes them easy to probe or solder to. We *do* make mistakes, so it's better for them to be easy to hack.

--
John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

I would if I ever had a 64-bit bus!

I had one guy who named a bus A[0:15] on one sheet and A[15:0] on another, a uP connecting to a 64K eprom. So we wrote an application that reordered the code image to correct for the address remapping.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

PADS Logic invents a unique name for any net that does not have a named offpage, like $$$23456.

I can add a named offpage to a net, with no other offpages, if I want to force a net name, so we can see it when we route or something. It works.

Again, what really matters is getting the first board right. We don't prototype products and we assume we'll sell rev A, the first etch. I know companies that formally define *five* PCB iterations and always use those five, and often more. Three year developments keep lots of engineers employed.

How many layout iterations do people here average?

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

John Larkin wrote in news: snipped-for-privacy@4ax.com:

Depends on what is being laid out.

RF may need a massage.

Logic may as well, if a lot of real estate is involved and trace length timings become an issue.

Sometimes signal timing can cause a respin requisite.

Power supplies can have hard start issues resolved with circuit changes. We had some FETs that we ended up putting a singular toroid core right onto the lead of the FET before insertion into the PCB.

That and adding things like transzorbs or the like. Sometimes the need for a circuit element in a design does not rear its head until after an initial iteration.

Reply to
DecadentLinuxUserNumeroUno

We design review the heck out of things, schematic and layout, and have checklists for both. We leave stuffing options or jumper hooks if we think there is any risk. It's a friendly sport to find mistakes in other peoples designs and layouts, so we manufacture very few dumb errors.

We do occasionally lay out a little test board for some tricky new subcircuit, but we don't prototype whole products.

My new guy just got his first PCB design all built. We made the classic mistake of swapping the V+ and V- power pins on two opamps, which is klugable but not pretty. He won't do that again. We should have caught that during a review, and my layout guy should have noticed it.

There are *so many* possible mistakes.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

mandag den 15. april 2019 kl. 16.09.55 UTC+2 skrev snipped-for-privacy@notreal.com:

rote:

in message

rant of

es usually

wouldn't run it. It took a few goes looking over it to notice I'd connected the power rails together via 2 base junctions. Oops. A base-ic error.

to

rts of

ence

s;

them

ool

en if

like

on

but afair you have to put labels on the pins you connect to a bus, the bus is just shorthand for getting a bunch of signals off a page without having to add a port for each and everyone

obal

in Kicad net labels default to hierachical, i.e. when you label a net the net name is in the netlist is /sheetname/netname

Reply to
Lasse Langwadt Christensen

We don't do hierachical schematics either! Every part and net is visible on the schematic and the board.

--
John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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Reply to
John Larkin

Is that an ebay bargain? Since you're only building one circuit, you might consider the NTE equivalent, NTE458, which you can buy from NTE direct:

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The generic subs aren't much of bargain if they're way out of spec and you have to buy a bunch of them. Apparently people have been plugging the NTE458 into 2SK117 circuits for quite a while, with no complaints.

Reply to
bloggs.fredbloggs.fred

I don't want to clutter up pages with unnecessary off-page connectors but I do like to name every net. It makes finding one's way around a layout much easier. I also try to get the layout engineer to have at least one segment of every (non-power) net on surface wiring, often fanning out from QFP/QFNs.

The checking in the designer forward annotation doesn't allow things like single pin nets.

I add a resistor to every unused PIO. I find it's a lot easier to wire to a resistor than a pad.

Reply to
krw

How could you not notice the problem when fanning out the bus?

I've done similar things but in the end it's more painful than it's worth.

Reply to
krw

Yes, but that's a different issue.

But it makes a mess of the schematic if you do a lot of them.

If you decide that there will be five iterations, you're lucky of you only have five, sure. our production groups a similar thing but it gets worse than that. THe reason they have several spins built into the schedule is more because the customer more or less demands it (they want a place to insert changes, too).

I generally do one but I only do prototypes. I do have three revs of my last design but they're really three different designs that only look similar. OTOH, my prototype run is probably larger than your normal production run. ;-)

Reply to
krw

mandag den 15. april 2019 kl. 20.25.22 UTC+2 skrev John Larkin:

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ce wouldn't run it. It took a few goes looking over it to notice I'd connec ted the power rails together via 2 base junctions. Oops. A base-ic error.

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global

why wouldn't they be just because it is hierarchical ?

Reply to
Lasse Langwadt Christensen

John Larkin wrote in news: snipped-for-privacy@4ax.com:

The ever-present reverse pinout on opamps... One must always make sure...

Reply to
DecadentLinuxUserNumeroUno

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