Tektronix purchased Keithley, broke my instruments?

I posted this earlier, but it hasn't shown up:

On re-reading the instruments paper, I discover that I misremembered--this gizmo didn't use the ring-down amplitude calibration scheme. I used that in another project about ten years later, which was another laser interferometer (a handheld 3-D scanner).

Cheers

Phil Hobbs

Yes, I was starting to get a bit confused. But what I was reading was still very interesting.

Any chance to get a copy of the later ring-down amplitude calibration scheme?

NB: I picked the wrong data point in the graph on page 12 of

I chose 60dB when it should have been 72dB. However, HP didn't do any calibration at 80MHz, so it is clear your method would have beat them by a large margin. I'd like to learn how you did it!

Thanks

Thank you. I'm sure that if I ever build the thing I will discover that I made several more serious mistakes than those already pointed out.

Plonk

Huh? What for?

Jeroen Belleman

On 7/9/19 6:26 AM, Steve Wilson wrote:

Something vaguely like this, but with a much longer ring-down. IIRC my actual one used a PIN diode rather than a pHEMT, but I just picked up a thousand ATF38143s on eBay for $300, so I have plenty for protos. ;) (Also for small production runs.)

To oscillator mavens: There are lots of sins in this oscillator design, but one needn't care because the oscillator isn't even in the circuit when the ring-down is occurring. So don't give me agita.

Cheers

Phil Hobbs

~~~~~~~~~~~~~~~~~~~~~~~ Version 4 SHEET 1 1400 680 WIRE -464 -96 -480 -96 WIRE -368 -96 -384 -96 WIRE 400 -96 -368 -96 WIRE 400 -80 400 -96 WIRE -464 -64 -464 -96 WIRE -368 -64 -368 -96 WIRE -128 -16 -240 -16 WIRE -16 -16 -128 -16 WIRE 224 -16 -16 -16 WIRE 288 -16 224 -16 WIRE 320 -16 288 -16 WIRE 352 -16 320 -16 WIRE -240 0 -240 -16 WIRE -16 16 -16 -16 WIRE 288 16 288 -16 WIRE -464 48 -464 16 WIRE -368 48 -368 16 WIRE -128 80 -128 -16 WIRE -240 96 -240 80 WIRE 288 96 288 80 WIRE 400 96 400 16 WIRE 400 96 288 96 WIRE 288 112 288 96 WIRE 400 112 400 96 WIRE -16 128 -16 96 WIRE 224 128 224 -16 WIRE -176 160 -256 160 WIRE -256 176 -256 160 WIRE 224 224 224 208 WIRE 288 224 288 176 WIRE 400 224 400 192 WIRE -256 272 -256 256 WIRE -16 288 -16 192 WIRE 96 288 -16 288 WIRE 112 288 96 288 WIRE 208 288 176 288 WIRE 304 288 288 288 WIRE 320 288 304 288 WIRE 464 288 400 288 WIRE 560 288 528 288 WIRE 656 288 640 288 WIRE 672 288 656 288 WIRE 816 288 752 288 WIRE 176 304 176 288 WIRE 528 304 528 288 WIRE -16 320 -16 288 WIRE -256 368 -256 352 WIRE -128 368 -128 176 WIRE 304 368 304 288 WIRE 320 368 304 368 WIRE 656 368 656 288 WIRE 672 368 656 368 WIRE 464 384 464 288 WIRE 464 384 384 384 WIRE 528 384 464 384 WIRE 608 384 528 384 WIRE 816 384 816 288 WIRE 816 384 736 384 WIRE 880 384 816 384 WIRE 112 400 112 288 WIRE 320 400 112 400 WIRE 608 400 608 384 WIRE 672 400 608 400 WIRE -16 416 -16 400 FLAG -368 48 0 FLAG -384 -96 +12 FLAG 400 224 0 FLAG 288 224 0 FLAG -16 416 0 FLAG -240 96 0 FLAG 224 224 0 FLAG -128 368 0 FLAG -256 368 0 FLAG -464 48 0 FLAG -480 -96 -12 FLAG 352 352 +12 FLAG 352 416 -12 FLAG 176 304 0 FLAG 704 352 +12 FLAG 704 416 -12 FLAG 528 304 0 FLAG 96 288 tap FLAG 528 384 o1 FLAG 880 384 out FLAG 320 -16 gate SYMBOL voltage -368 -80 R0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL ind 0 112 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L1

SYMBOL cap 272 112 R0 SYMATTR InstName C1 SYMATTR Value 8p SYMBOL cap 272 16 R0 SYMATTR InstName C2 SYMATTR Value 12p SYMBOL njf 352 -80 R0 SYMATTR InstName J1 SYMATTR Value 2N4416 SYMBOL res -32 304 R0 SYMATTR InstName R2 SYMATTR Value 4 SYMBOL current -240 0 R0 WINDOW 3 -60 -119 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(0 1m 1u 1n 1n 100n) SYMATTR InstName I1 SYMBOL cap -32 128 R0 SYMATTR InstName C3 SYMATTR Value 10f SYMBOL res 240 112 M0 WINDOW 0 52 72 Left 2 WINDOW 3 36 99 Left 2 SYMATTR InstName R4 SYMATTR Value 10Meg SYMBOL mesfet -176 80 R0 WINDOW 0 63 67 Left 2 WINDOW 3 -179 62 Left 2 SYMATTR InstName Z1 SYMATTR Value ATF38143_chip SYMBOL voltage -256 256 R0 WINDOW 3 -311 91 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(-5 3 100u 1n 1n 1) SYMATTR InstName V2 SYMBOL res -272 160 R0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL current 400 112 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName I2 SYMATTR Value 10m SYMBOL Opamps\\LT1260 352 320 R0 SYMATTR InstName U1 SYMBOL voltage -464 -80 R0 SYMATTR InstName V3 SYMATTR Value -12 SYMBOL Opamps\\LT1260 704 320 R0 SYMATTR InstName U2 SYMBOL res 656 304 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 -7 114 VBottom 2 SYMATTR InstName R1 SYMATTR Value 1.5k SYMBOL res 544 304 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 300 SYMBOL res 304 304 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 -7 114 VBottom 2 SYMATTR InstName R6 SYMATTR Value 1.5k SYMBOL res 192 304 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R7 SYMATTR Value 300 TEXT -536 288 Left 2 !.tran 300u TEXT 472 -96 Left 2 !.MODEL ATF38143_chip NMF( vto=-0.75, Beta=0.3, Lambda=0.07, Alpha=4,\n+ B=0.8, Pb=0.7, Cgs=0.997E-12,\n+ Cgd=0.176E-12, Rd=0.084, Rs=0.054, Kf=1e6, Af=1) TEXT -368 88 Left 2 ;Kickstart TEXT 544 88 Left 2 ;Crystal Ring-down Calibrator\n(General idea--real XOs ring down \na lot more slowly than this)\n \nPH 7/10/19 TEXT 848 288 Left 2 ;Leading error term goes as \n(slew/max slew)**3 TEXT -280 -72 Left 2 ;Need to make crystal oscillate at \nits series (mechanical) resonance TEXT 16 16 Left 2 ;Resonate Cpar\naway with Lpar

Thanks for the lovely ASC file. That shows how to generate a damped sine wave. I especially appreciate your labels on the critical nodes. I wish more people did that.

I was hoping to find out how you sampled the ringdown signal to get 12 digits of accuracy, especially with the devices that were available at the time. That is a big mystery to me.

Thanks for your help.

In my thesis project, the Plessey DLVA building blocks produced a logarithmically compressed AC waveform, which I full-wave rectified with a Mini Circuits transformer and a couple of Schottky diodes. The resulting DC went into an op amp and then into a 12-bit digitizer (iirc it was an AD ADC12something, but I no longer have the datasheet).

In the 1998ish project that used the ring-down trick, IIRC I was using two cascaded Motorola MC3357 FM IFs, which had direct current-mode RSSI outputs that I wired together into a common-base PNP stage. Turned out that if you cascoded them like that, they sped up amazingly--I was getting 40-ns edges, which helped a lot with the application. RIP.

Cheers

Phil Hobbs

I think it was another DAC80/AD2504 SAR ADC.

Cheers

Phil Hobbs

Oh well, it will save me the time of replying to him, so win-win I guess :-)

Illumination! Thanks.

I'm still a bit confused. I found the MC3357 Datasheet at

It shows the device running at 10MHz, with a 5 stage limiter.

I thought FM IF limiters were used to provide a constant amplitude output over a wide range of input signal amplitudes.

How can you get a limiter to provide a logarithmic output that you can feed into a rectifier to measure ringdown?

Mystified.

I didn't notice the RSSI output. However, I can't find any kind of signal strength indication on the MC3357 datasheet. Did I get the wrong datasheet?

Sorry, another misremembered fact. I think it was actually the MC13055. (I had to leave my lab notebooks behind when I left IBM, unfortunately. They probably threw them out.) :(

The RSSI (Received Signal Strength Indicator) output is logarithmic within about a decibel over a pretty wide range, if you get the inter-stage attenuation right. If you cascade too many stages the noise starts to dominate, so the log conformance suffers.

You can see how it works from Fig 15 of the MC13055 datasheet. There are several cascaded differential pairs, driven by current sources, and each having an extra transistor hung off the common emitters that generates a current proportional to the positive-going excursion of the CE node. Those currents are summed and mirrored before going out the RSSI pin.

While a given pair is in its linear range, the emitters hardly move at all. When it starts to reach cutoff on the negative swings, the transistor on the positive-going half cycle drags the emitter node along with it, generating more RSSI output current but no more output voltage because the current source doesn't provide any more current. When the previous stage saturates, the RSSI contribution maxes out, so the overall gain drops by the gain of that stage. Thus for 10-dB stage gains, your gain drops by 10 dB for every 10 dB signal increase, so

dVout/dVin ~ 1/Vin

which is the differential equation for a logarithm. Pretty slick actually.

Cheers

Phil Hobbs

Pretty amazing that you are able to remember after all these years.

Thanks for the analysis and for all the time spent on this problem. Your information is priceless and could not be obtained anywhere else.

Steve

Unlikely. The US was first-to-invent at that time. They had to keep the notebooks for patent enforcement, and probably sent them to the attorneys. They are probably still there for investigation of prior art. You are immortal!