TDA21106

This MOSFET driver is designed to drive one low-side n-FET switch, and one high-side n-FET switch. It says that on page two of the datasheet.

To turn on an n-FET, you must bring Vgs greater than some large positive value, typically around 10 V (though it could be lower for "logic-level" FETs). To turn the FET off, bring Vgs less than the "threshold voltage", so less than a volt or so.

Consider an (artificial) example circuit:

/|\ Vsupply > 0 | | |----+ | | | | Vsupply + (10 V). That means that the voltage that you apply to the high-side gate has to be higher than the supply voltage. For example, if Vsupply = 12 V then you have to apply 22 V to the gate of the high-side FET to turn it on.

That is the purpose of the "boostrap" circuit. The FET driver uses a switched capacitor circuit to derive the higher gate drive voltage from the input voltage.

FET drivers do other things too. For example, the circuit that drives the gates of the FETs has a very small output impedance. That allows the FET driver to charge and discharge the FET gate capacitance very quickly, so that the FETs switch quickly, to reduce the power dissipation in the FET while switching. The FET driver will also make sure that you don't turn on the high- and low-side switches simultaneously (since that effectively short-circuits your power supply).

Jonathan

Thanks Jonathan for your precious assistance. Immagine for example we're working with mosfet IRF3205 in switching mode 20KHz. As data sheet says Qgmax=146nanocoulomb, I calculate Idriver=146nc*20KHz=2,9milliAmp but this value seems to me too low ! What am I missing ? Referring the IRF3205, is correct the dinamic power losses calculation as P=(tfall+trise)*20Khz= (lookink at tf and tr datasheet value)=(100nanosec+70ns)*20Khz=3,4mW.

thanks in advance

mauri

The gate current is not constant over a clock cycle.... You want to turn the FET on and off as quickly as possible. The gate current should look like a big spike (up or down) every time the gate voltage makes a transition, and zero otherwise.

The FET driver current is determined more by the FET driver than by the FET. Immediately after the gate drive voltage makes a transition, the gate capacitance looks like a dead short circuit, so the current is limited only by the FET driver's output impedance. The current falls to close to zero as soon as the FET's gate capacitance is close to fully charged/discharged.

I would say no. The units don't work: ns*kHz = 10^(-6) dimensionless, not watts, so that must be completely wrong.

The rise/fall times in the IRF3205 datasheet are under the given set of assumptions. They will depend on the gate driver used (or in this case since Rg was fairly large when they made the measurement, on the resistance Rg in series with the gate). If you added more resistance in series with the gate then the times would get slower. If you reduced the impedance of the voltage source driving the gate then the times would get faster.

I don't know a good way to calculate switching losses from the specs that are usually given in the datasheets. International Rectifier has some interesting new specs that should supposedly make things easier; see for example the IRF7807 datasheet, with their Qgs1/Qgs2 method.

Jonathan