Switching Regulator Efficiency vs. Load Current

I'm trying to understand why the efficiency of a switching regulator reduces dramatically as the load current reduces, while it stays high and relative flat when load current is large. The initial reason I cooked up was this:

efficiency ~ Pout/Pin. Pout = Vout*Iout, Pin = Vin*Iin If Vout and Vin are relatively constant, and average input current is also relatively constant (Its actually pulsing I guess, but I'm ignoring that), then the efficiency should linearly increase with Iout.

The problem is this - the efficiency doesn't depend linearly at all on the load current. Most graphs I've seen seem to look like a log function on linear axes (i.e. growing rather quickly as load current increases from zero, and then flattening out for higher currents).

So can anyone suggest any reasons why the curve looks like this? Here is an explanation that is brewing currently in my head - I believe the switching losses in the FET are largely dependent on the switching frequency and rather independent of the load current. I've also heard that this switching loss comprises most of the regulator loss. Is that true? If that's the case, then I would assume the other losses become more and more significant as the output power reduces, so for higher output power, the switching loss being dominant makes the curve flat, which for lower and lower output power, the other losses start becoming dominant. Have I hit the nail on the head here? If not, can someone please clarify this issue...Thanks!

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The problem with your argument is that the average input current depends on the average output current. It is not "relatively constant".

Reply to
DJ Delorie

Consider that whatever controller you use will draw nearly constant power, if the switching frequency stays constant. That overhead exists even when the output power goes to zero. That's pretty close to what you've said in your closing paragraph. There's significant power used in just driving the gate of the FET, and as you note, there's power associated with the drain circuit switching and with the transformer core cycling through its hysteresis loop and with some other similar things. V*I in the FET during its on time is typically reduced, because with lower output, either the FET current and voltage drop are lower or the duty cycle is lower, or both.

Bring up LTSpice/Switcher Cad III, and you can explore some of these things through simulation. LTSpice lets you get a report on just where the power is going, if you want, and all the Linear Technology switcher chips have included models.

Note that some controllers go to lower frequency (skip cycles) at low output power, so the power-hungry cycles that aren't necessary to maintain the output voltage at low load are eliminated. If they've done other things right, the efficiency will hold up better at low load than with other controllers that keep cycling unnecessarily.

Cheers, Tom

Reply to
Tom Bruhns

These may be controllers that go into a "burst mode" operation at low output levels, which works well when output regulation and ripple are not highly critical. I found that some switching regulators do this, perhaps unintentionally, with certain combinations of output capacitance and compensation capacitance. Burst mode works best when the controller and MOSFET driver can be put into a low power mode during the off times.

Some power supplies require a minimum load, and capacitors need some sort of bleeder resistor, so these may also contribute to less efficiency at low loads.

But I think switching losses are the big item, which is a fairly constant power at all duty cycles, while conduction losses are what increase with load, and limit the efficiency at the high end.


Reply to
Paul E. Schoen

If this is a buck regulator, it would also be useful for him to see what happens at low currents if he makes the inductor bigger.


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