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SPI transmission line thing

I need to feed an SPI clock to eight isolated channels, using ADUM1400 isolators spaced about 0.8" apart, in a straight line. It's not easy to get a clean logic drive to that string, for some reason.

The following is all wrong, but it works.

One trick is to use a slow buffer, an HCT244, to avoid a lot of ugly reflections and make it less wrong.

Version 4 SHEET 1 1684 784 WIRE 64 -32 48 -32 WIRE 96 -32 64 -32 WIRE 208 -32 176 -32 WIRE 224 -32 208 -32 WIRE 48 16 48 -32 WIRE 48 128 48 96 WIRE 320 128 256 128 WIRE 224 160 224 -32 WIRE 256 160 256 128 WIRE 256 272 256 256 WIRE 320 272 320 128 WIRE 320 272 256 272 WIRE 320 320 320 272 WIRE -1152 512 -1184 512 WIRE -1072 512 -1152 512 WIRE -880 512 -976 512 WIRE -848 512 -880 512 WIRE -736 512 -848 512 WIRE -544 512 -640 512 WIRE -496 512 -544 512 WIRE -384 512 -496 512 WIRE -160 512 -288 512 WIRE -112 512 -160 512 WIRE 16 512 -112 512 WIRE 192 512 112 512 WIRE 224 512 224 256 WIRE 224 512 192 512 WIRE 336 512 224 512 WIRE 560 512 432 512 WIRE 640 512 560 512 WIRE 752 512 640 512 WIRE 944 512 848 512 WIRE 1024 512 944 512 WIRE 1088 512 1024 512 WIRE 1280 512 1184 512 WIRE 1328 512 1280 512 WIRE 1424 512 1328 512 WIRE 1584 512 1520 512 WIRE 1616 512 1584 512 WIRE -1072 544 -1088 544 WIRE -960 544 -976 544 WIRE -736 544 -752 544 WIRE -624 544 -640 544 WIRE -384 544 -400 544 WIRE -272 544 -288 544 WIRE 16 544 0 544 WIRE 128 544 112 544 WIRE 336 544 320 544 WIRE 448 544 432 544 WIRE 752 544 736 544 WIRE 864 544 848 544 WIRE 1088 544 1072 544 WIRE 1200 544 1184 544 WIRE 1424 544 1408 544 WIRE 1536 544 1520 544 WIRE -1184 576 -1184 512 WIRE -1088 576 -1088 544 WIRE -1024 576 -1088 576 WIRE -960 576 -960 544 WIRE -960 576 -1024 576 WIRE -848 576 -848 512 WIRE -752 576 -752 544 WIRE -688 576 -752 576 WIRE -624 576 -624 544 WIRE -624 576 -688 576 WIRE -496 576 -496 512 WIRE -400 576 -400 544 WIRE -336 576 -400 576 WIRE -272 576 -272 544 WIRE -272 576 -336 576 WIRE -160 576 -160 512 WIRE 0 576 0 544 WIRE 64 576 0 576 WIRE 128 576 128 544 WIRE 128 576 64 576 WIRE 320 576 320 544 WIRE 384 576 320 576 WIRE 448 576 448 544 WIRE 448 576 384 576 WIRE 640 576 640 512 WIRE 736 576 736 544 WIRE 800 576 736 576 WIRE 864 576 864 544 WIRE 864 576 800 576 WIRE 944 576 944 512 WIRE 1072 576 1072 544 WIRE 1136 576 1072 576 WIRE 1200 576 1200 544 WIRE 1200 576 1136 576 WIRE 1280 576 1280 512 WIRE 1408 576 1408 544 WIRE 1472 576 1408 576 WIRE 1536 576 1536 544 WIRE 1536 576 1472 576 WIRE 1616 576 1616 512 WIRE -1024 624 -1024 576 WIRE -688 624 -688 576 WIRE -336 624 -336 576 WIRE 64 624 64 576 WIRE 384 624 384 576 WIRE 800 624 800 576 WIRE 1136 624 1136 576 WIRE 1472 624 1472 576 WIRE -1184 688 -1184 640 WIRE -848 688 -848 640 WIRE -496 688 -496 640 WIRE -160 688 -160 640 WIRE 640 688 640 640 WIRE 944 688 944 640 WIRE 1280 688 1280 640 WIRE 1616 688 1616 640 FLAG 48 128 0 FLAG -496 688 0 FLAG -160 688 0 FLAG 640 688 0 FLAG 944 688 0 FLAG -336 624 0 FLAG 800 624 0 FLAG 1280 688 0 FLAG 1136 624 0 FLAG 1616 688 0 FLAG 1472 624 0 FLAG -848 688 0 FLAG -688 624 0 FLAG -1184 688 0 FLAG -1024 624 0 FLAG 320 320 0 FLAG 64 -32 G2 FLAG -1152 512 A FLAG -880 512 B FLAG -544 512 C FLAG -112 512 D FLAG 560 512 E FLAG 1024 512 F FLAG 208 -32 T2 FLAG 64 624 0 FLAG 384 624 0 FLAG 1328 512 G FLAG 1584 512 H FLAG 192 512 TEE SYMBOL voltage 48 0 R0 WINDOW 0 -69 5 Left 2 WINDOW 3 -376 63 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 3.3 2n 7n 7n 10n) SYMBOL res 192 -48 R90 WINDOW 0 -59 51 VBottom 2 WINDOW 3 -47 54 VTop 2 SYMATTR InstName R1 SYMATTR Value 35 SYMBOL cap -176 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C1 SYMATTR Value 4p SYMBOL tline 800 528 R0 WINDOW 0 -1 -72 Bottom 2 WINDOW 3 1 -64 Top 2 SYMATTR InstName T2 SYMATTR Value Td=120p Z0=90 SYMBOL cap 624 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C2 SYMATTR Value 4p SYMBOL tline -336 528 R0 WINDOW 0 3 -78 Bottom 2 WINDOW 3 6 -69 Top 2 SYMATTR InstName T3 SYMATTR Value Td=120p Z0=90 SYMBOL cap 928 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C3 SYMATTR Value 4p SYMBOL cap -512 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C4 SYMATTR Value 4p SYMBOL tline 1136 528 R0 WINDOW 0 -1 -72 Bottom 2 WINDOW 3 1 -64 Top 2 SYMATTR InstName T4 SYMATTR Value Td=120p Z0=90 SYMBOL cap 1264 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C5 SYMATTR Value 4p SYMBOL tline 1472 528 R0 WINDOW 0 -1 -72 Bottom 2 WINDOW 3 1 -64 Top 2 SYMATTR InstName T5 SYMATTR Value Td=120p Z0=90 SYMBOL cap 1600 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C6 SYMATTR Value 4p SYMBOL tline -688 528 R0 WINDOW 0 3 -78 Bottom 2 WINDOW 3 6 -69 Top 2 SYMATTR InstName T6 SYMATTR Value Td=120p Z0=90 SYMBOL cap -864 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C7 SYMATTR Value 4p SYMBOL tline -1024 528 R0 WINDOW 0 3 -78 Bottom 2 WINDOW 3 6 -69 Top 2 SYMATTR InstName T7 SYMATTR Value Td=120p Z0=90 SYMBOL cap -1200 576 R0 WINDOW 0 45 14 Left 2 WINDOW 3 46 47 Left 2 SYMATTR InstName C8 SYMATTR Value 4p SYMBOL tline 240 208 R90 WINDOW 0 -7 100 Bottom 2 WINDOW 3 0 26 Top 2 SYMATTR InstName T8 SYMATTR Value Td=2n Z0=40 SYMBOL tline 64 528 R0 WINDOW 0 3 -78 Bottom 2 WINDOW 3 6 -69 Top 2 SYMATTR InstName T1 SYMATTR Value Td=60p Z0=90 SYMBOL tline 384 528 R0 WINDOW 0 3 -78 Bottom 2 WINDOW 3 6 -69 Top 2 SYMATTR InstName T9 SYMATTR Value Td=60p Z0=90 TEXT 528 168 Left 2 ;4 pF caps represent ADUM1400 isolators TEXT 744 112 Left 2 !.tran 0 30n 0 5p TEXT 584 8 Left 2 ;P470 Clock Distribution to ADUM Isolators TEXT 696 48 Left 2 ;J Larkin Aug 20, 2015 TEXT 584 256 Left 2 ;T2-T7 are 6 mil 90 ohm traces, 800 mils long TEXT -320 112 Left 2 ;2 or 3 sections of 74HCT244 TEXT 720 216 Left 2 ;T8 is feeder trace TEXT -288 152 Left 2 ;Vcc = 3.3 Tr = 7ns TEXT -392 200 Left 2 ;R1 will include HCT244 impedances

--

John Larkin         Highland Technology, Inc 
lunatic fringe electronics 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin
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Yeh, what clock frequency?

Glancing at the listing, I suppose you've modeled the traces as transmission lines of typical impedance? If you can gloss over the mismatch (alternating high impedance transmission lines and shunt capacitances or low impedance lines look like a lowpass filter), then the average impedance can be terminated (source and/or load) and overshoot/ringing will be minimal. The transition itself might be ugly (a lumpy rise, due to reflection and loss in the LPF structure, and due to the effect of source termination), but if it's still fast enough, who cares?

Are those eight channels actually critical in regards to timing / jitter, or do they not matter?

Tim

-- Seven Transistor Labs Electrical Engineering Consultation Website:

formatting link

Reply to
Tim Williams

That doesn't matter; only edge quality matters.

6 mil traces on the top of a 6-layer board, with L2 being the ground plane. 88 ohms according to AppCad.

If you can gloss over the mismatch (alternating

That's the heart of the problem: the transmission line traces are periodically loaded with lump capacitances. Driven by slow edges, you can pretend that it's just a lower impedance line. But drive it with fast edges, it's a ringing nightmare.

End termination requires an insanely brute driver to avoid voltage loss, especially in the tee config. Driving one end and terminating the other got ugly. Source termination solves some problems.

The

Yup, it seems to work. Design by instinct and simulation.

They are SPI links up to isolated DACs, and we can have all the data setup/hold time we want, so relative alignment doesn't matter. We're simulating thermocouples, so there's no rush.

I should use HC244s at 3.3 volts, not HCTs. The HCT comment was left over from another version that didn't work as well, namely 5 volt drive with both source and end terminations to wind up with 3.3.

The design is messy in that we have to keep chasing the layout guy to make sure our clock terminations are compatible with his placement and routing.

--

John Larkin         Highland Technology, Inc 
lunatic fringe electronics 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

If this is a conventional clock, why not use a conventional multi-output clock driver? Or is this a gated clock?

--

Rick
Reply to
rickman

SPI clock, so I'll assume burst of clock when ever there is a transaction with the other end

a series resistor source termination(ish) is usually how it's done

-Lasse

Reply to
Lasse Langwadt Christensen

The series resistor only helps with part of the problem. It would be useful to prevent the load reflections as well. I think with a lower trace impedance the input capacitances have smaller reflections. The reduced drive is mitigated by *not* using a series resistor on the driver. Typical output impedance is much less than 50 ohms so that a 50 ohm terminator can be driven by many outputs and maintain TTL levels if that is what is needed. But every case is different.

The burst clock is only required if you are driving one SPI load with the enable always asserted. If you are driving multiple devices the enable needs to be used... unless you are driving them as one long SPI load. Again, every case is different. Using an always running clock would solve the clock distribution problem easily.

--

Rick
Reply to
rickman

Source termination shouldn't work with multiple loads along a line. It does if you slow down the drive some.

Driving my setup from one end works, too, but the tee drive is prettier.

CMOS keeps getting faster. The AHC and VHC and Tiny parts, and FPGAs, can output crazy edges, like 600 ps, and that can cause all sorts of problems.

Reply to
John Larkin

Den fredag den 21. august 2015 kl. 20.33.25 UTC+2 skrev John Larkin:

yes it is not so much termination as it is taming the edge to the point that isn't an issue

yes, fpgas and many mcus now have setting on how hard to drive IOs

-Lasse

Reply to
Lasse Langwadt Christensen

but give you a whole of other problems the clock is generally not always running when you use a SPI peripheral, never if you bit-bang. SPI is far from a standard and some devices have all sorts of limits on what you can do when

-Lasse

Reply to
Lasse Langwadt Christensen

If an SPI device uses the select line, then it has to ignore a free running clock by definition.

--

Rick
Reply to
rickman

FPGAs are often the cure for fast edges since they can be programmed for edge rate and drive strength.

--

Rick
Reply to
rickman

sure, but it might require a certain delay from enable to clock, extra delays when switching direction, delay from last clock to disable, etc.

about the only thing standard about SPI is the three letters, especially with stuff like ADCs

-Lasse

Reply to
Lasse Langwadt Christensen

The clock line is the only signal that we need to be careful with. MISO and MOSI can be routed any old way and be ugly as sin. The chip selects are star connections, easy to do right.

Reply to
John Larkin

Den fredag den 21. august 2015 kl. 21.47.11 UTC+2 skrev John Larkin:

yes, the getting everything to see the correct number of clock edges is the important part, data has time to settle

-Lasse

Reply to
Lasse Langwadt Christensen

Can you feed it through a bus driver IC that has a slew-rate control?

Reply to
DemonicTubes

How about skinny serpentine traces so the reflections all arrive at once, with the correct impedance? That would basically turn it into a single drop, so you could just series-terminate at the driver.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

I don't follow what you are saying.

--

Rick
Reply to
rickman

If you have, say, a 30-ohm trace, and split it into eight 240-ohm traces, either all at once (30 ohm -> 8x 240 ohm) or one at a time (so that at the forks the main trace goes 30 -> 34.3 -> 40 -> 48 -> 60 -> 80

-> 120 -> 240 ohms respectively), there are ideally no reflections at the splits.

If the branch lengths are chosen so that the reflections all arrive back at the driver at once, then at that end you have the usual series-termination, resulting in no ringing.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

I figured that a couple of paralleled HC240 sections would be about right. Risetime is about 7 ns or so. They are cheap and we have them.

One could use a modern fast part and add an LC lowpass, but that's getting silly.

Reply to
John Larkin

Can you really implement 240 ohm (unbalanced) PCB tracks ? The tracks would have to be really narrow.

The classical Wilkinson power divider will require a 1/4 wavelength traces between each power division points.

Reply to
upsidedown

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