I have a board where I want to use four small mosfets in parallel, to switch 100 volts or so in 2 ns or less, into 50 ohms. One gets speed here by stressing small fets, sot23 or super-sot6 packages. The problem becomes how to get the heat out. So I was wondering how much heat we can dump into the PCB ground plane. Candidate numbers are
4 fets4 layer board, 1 oz copper, L2 ground plane
12 mils of FR4 from top to ground plane1 watt target dissipation, more if possible
Topside drain pour about 600 x 250 mils
So, what's the thermal situation? The pour area is so small that we can ignore convection; 0.15 square inches at maybe 150k/w per, is 1000 k/w.
So most of the heat travels through the FR4 to the ground plane. Using published values (conductivity of the epoxy-glass at 0.27 w/m-k) and doing a simplistic calculation, the theta between the drain pour and the ground plane is around 10 k/w. Not bad at all, and the capacitance is tolerable.
But then there's the thermal spreading resistance of the ground plane, not so easy to calculate. Time for copperclad and x-acto knives.
ftp://jjlarkin.lmi.net/T750_t1.JPG
ftp://jjlarkin.lmi.net/T750_t2.JPG
ftp://jjlarkin.lmi.net/T750_t3.jpg
ftp://jjlarkin.lmi.net/T750_t4.jpg
ftp://jjlarkin.lmi.net/T750_t5.jpg
The kapton tape is black in the thermal IR, allowing me to thermally image the thing. The copper is a nearly perfect mirror, so all I'd see is the room ambient reflected.
P = 1 watt total
As expected, theta through the board is right around 10 k/w. But the bottom of the board (t5 above) is about 10k or so above ambient, so net theta is around 20k/w. Tolerable.
If I want to decrease theta without adding capacitance, I think I could add pours to additional layers, specifically L4, and use lots of vias to thermally stitch to the L2 ground plane; that would reduce the thermal spreading resistance.
What would be nice would be a board material with high thermal conductivity and low dielectric constant.
FR4 0.27/4.6 = 0.058
BeO 300/6.7 = 44.8
John