SMPS switching loss question

Hi,

In a buck regulator with a rectifier diode if: a. I use a driver of size 'X' to drive the control nmos (top nmos) of area 'Y' b. I use a driver of size 'X/2' to drive a control nmos (top nmos) of area 'Y/5'

Will the switching losses (due to Vds Id overlap) be less in case 'b' during turnon? Will the switching losses (due to Vds Id overlap) be less in case 'b' during turnoff?

I thought that the answer to both these questions should be yes, but in simulaton I find that during turn on the 'overlap' time during turnon is actually higher in case b as compared to case a. Is this expected in a real world situation? Why is this so ?

Thanks QQ

Reply to
QQ
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This isnt "homework". Just trying to get some understanding and didnt know anyone else to ask.

Thanks QQ

Fred Bartoli wrote:

Reply to
QQ

"QQ" a écrit dans le message de news: snipped-for-privacy@g47g2000cwa.googlegroups.com...

In a real homework situation, are you expected to cheat and have your work done by others?

Look a bit harder and light will come.

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Thanks,
Fred.
Reply to
Fred Bartoli

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