Just to give some feedback to the thread after some more experiments: the FET in question at the beginning, from the Maxim app-note, had a gate-capacitance of 882 pF, well beyond the rated maximum stable load of the op-amp of 200 pF. Various schemes were proposed to deal with that. Well I bought some FET's with 1/10th of the gate capacitance and I increased the output capacitor by a factor of 10 and this removed the oscillations on most driving points (although it seemed to appear in some still). I haven't tried the extra AC-feedback. This works well enough for me to continue the rest of the design meanwhile at least.
Seems like the phenomenon is a standard control-theoretic problem and should be treated as such, of course. I'm a theoretical guy so I would want to be able to spice-simulate this, but I couldn't get the oscillation to appear in the spice model.. oh well. Perhaps it is dependent on some noise being present to trigger the resonance in the feedback loop.
The reason the oscillation is sawtooth-shaped isn't it probably because the op-amps output-stage is asymmetric with regards to sinking and sourcing current to the FET-gate? It desperately tries to correct the input difference, and it has to charge the gate, the conductance changes, it has to discharge the gate etc. all this happening at different rates =3D> sawtooth.
I went and ordered a book dedicated only to voltage and current- sources, which will be interesting to read :)
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