Sawtooth-shaped oscillation from op-amp buffer?

Well, the data sheet says you shouldn't load the output with more than

The output resistance of the amp times the capacitive load puts an RC lowpass pole into the feedback loop. That's often enough to make even unity-gain stable amps oscillate. The usual trick is to put a resistor in series with the load. If you need better DC accuracy than that will give you, you can take the DC feedback from the load capacitor and the AC feedback from the op amp output.

Cheers,

Phil Hobbs

Hey Phil, can about I buy you a coffee?

D from BC myrealaddress(at)comic(dot)com British Columbia Canada

Ah yes, a trick from the National analog book.

Yup--Widlar's AN4, from 1968--still good reading after 40 years. It's Figure 15--see

Cheers,

Phil Hobbs

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The strange thing is that my circuit (when it included the FET-buffer) is a verbatim copy of this article written by Ken Yang of Maxim in EDN:

title is "Ultra-low-noise low-dropout regulator achieves 6-nv/sqrt(hz) noise floor". In this he explicitely breaks the

Ok then...

Supply bypass?

Tim

-- Deep Friar: a very philosophical monk. Website:

Very strange (strangest part is that a guy from Maxim designs an app- note for their own op-amps which might be inherently unstable). Perhaps I should mail him and ask...

/Bjorn

It's not strange, it's *typical*. Don't blindly trust application note circuits, *ever*! I get the impression they are done by junior engineers, fiddling around in the lab to make interesting circuits, and not always checked all that well. You are not the first one to be burned!

A "trick" I've known since I was a kid ;-)

...Jim Thompson

Are you sure you have the opamp inputs the right way around? The circuit you posted a link to had the *negative* input driven from the reference. (The external P-Fet inverts the feedback, so you need to use the opamp inputs the opposite way around than usual).

Failing that, did you try Phil Hobbs advice about AC feedback from the opamp output and DC from the P-Fet output?

Right, because you didn't take the feedback from *before* the resistor--adding extra resistance that way looks just like increasing the op amp's output resistance. A better method in this case would be to add an emitter follower between the op amp and the FET.

One of the best pieces of advice I ever received was as a teenager--I was told, "You can learn a lot of electronics by assuming that all application note circuits are bad, and figuring out how to fix them." I indeed learned a lot of electronics that way.

It's sort of the advanced course--if you can see the jokes in all of H&H's 'bad circuits', the next level is doing the same thing to app note circuits.

BTW many of the mistakes there are of the sort you're seeing here--things that work great some of the time but not always, due to exceeding guaranteed limits on common mode ranges, load capacitance, and so on. Others I've seen are startup problems, bias shifts in large signal operation, and a tendency to turn into lava at low or high supply voltage.

Cheers,

Phil Hobbs

Speaking of jokes, the PNP collector driving an NPN base thru a series resistor, with no pull-down path, in the thread, "What Oscillator is in This PS?", takes this week's grand prize.

...Jim Thompson

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Damn those guys were good. There is also that trick with the high speed buffer in the "can" where you solder the output to the can to reduce input capacitance. They were both smart and practical.

National never gave the analog guys much respect, hence the creation of Linear Technology. It is no coincidence that their engineering building has a sign outside that says "Home of the Gurus". Though I worked for the competition at the time, I had and still have great respect for their designers.

This is how it's done:

| |\\ ||-+ --------|+\\ ___ ||-> Q1 | >---o---|___|-----||-+ .----|-/ | | | |/ | R1 o------>

| | | | C1 --- | | --- .-. | | | | R2 | | | | | | '-' | | | '-----------o----------------o | .-. | | R3 | | '-' | | === GND (created by AACircuit v1.28.4 beta 13/12/04

R1 keeps the FET from loading from the op-amp, and C1 eliminates (destabilizing) R1 * Cgs(Q1) feedback delay.

Cheers, James Arthur

The FET in the OP's circuit is running common source, with feedback going to the + input of the op amp. Because the FET is an inverting stage, the split feedback trick doesn't work in this simple form.

Cheers,

Phil Hobbs

Oops, I biffed the ASCII drawing. Thanks for the catch. Corrected, above.

It doesn't have the low-dropout, but should still let the op amp cancel Q1's noise.

Cheers, James Arthur

The source follower bootstraps the Cgs anyway, so it shouldn't need the split feedback as badly. It also doesn't have the low-dropout feature--one might as well use an LM317. Something like an emitter follower driving the FET would be the ticket.

Cheers,

Phil Hobbs

Or, to keep the low drop-out, why not: V+ -+- || Ca | .---||---. | | || | ||--+ | | | | ___ | |\\ | ||->' Q1 ...----o----|___|---o--|-\\ | ___ | | Ra | >--o-|___|--||--. C1 --- .--|+/ Rb | 100uF--- | |/ o----->

| | | === | .-. GND | | | R2 | | | 3.9k | '-' | | '---------------------o | .-. | | R3 | | 2.4k '-' | === GND

(created by AACircuit v1.28.4 beta 13/12/04

The (+) input already sees R3 || R2 = 1.5k, so a smallish Ra shouldn't wreck the noise performance.

Cheers, James Arthur

That might work fine, depending on the gain of the FET/output bypass/load resistance system. The (Z0+Rb)Cgs pole is still inside the outer loop, and the noninverting gain doesn't drop below 1.0 even with the integrator. That can be fixed by adding enough output bypass capacitance that the outer feedback loop is stable regardless of load. Getting the transient response to be decent will be a bit of a problem, but then I think pretty much all LDOs have that difficulty.

Cheers,

Phil Hobbs