Sample & hold error

Sure, at least in a lab.

Leakage from all sources has to be in the low tens of pA.

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Bwahahahahahaha ;-)

I laughed, then I further realized, Larkin has no proper tools to verify layout versus schematic ??????

Sheeeeeesh! ...Jim Thompson

Well, my point exactly!

But it's kinda cool. Big, 8 layers, with a 750 ball BGA, PCI Express, and a 260 MHz ARM processor.

The box that this goes in has 68 connectors to the outside world.

John

I know that they had gotten to 10 bits but differential offset was giving them serious pain. I think someone once had a laser trimmed hybrid at 12 bits, but price tag and yields were giving them fits.

I can't seem to recall any time when you admitted an error, lots of professions of perfection though.

Not unless i get to compare it to the schematic, otherwise there is scant point.

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Yes, the 2nd idea I began looking at was seeing if I could get my crude comparator device to work in a similar way, using an analogue signal to get it to count upward, comparing its analogue output with the analogue input to get the analogue count up/down signal. I've had to go do other things, but will hopefully get back to that soon.

NT

I want this to work in a rented domestic environment subject to the usual mild abuse, including damp, knocks etc, and want it cheap & simple if possible. Minimising development time is more important than BOM, as only a few will be made. Commercial ICs fall far short of the holding ability required, which is the one key spec. So I admit to lacking confidence in the usual capacitor approach.

Looks like I'll go for the counter option, as soon as I get a bit more time to work on this. Thanks everyone!

NT

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A 3-chip (plus a lot of work) solution: a quad SPI ADC, a quad SPI DAC, and a little CPLD.

Or an ARM with ADC and PWM.

Or do it analog.

John

Thank you, I've emailed.

Today I've been unsidetracked with something else, but more ideas are brewing on the simple comparator approach, when I get tiem I'll sim attempt 2.

NT

The 'commercial ICs' for sample/hold are intended for short measurement cycles, their virtues aren't the ones you require. The tracking DAC (clock, up/down counter, DAC, comparator to switch up/down) has slew limits but once you inhibit the clock it holds forever. The big-hold-capacitor ALSO has slew limits and can hold well enough-for hours.

If it takes an IC labeled as the solution to your problem to inspire confidence, you just may be doomed. You have an unusual problem.

This hasnt been forgotten, as sometimes happens other things have been taking priority so far.

NT