RIS-660A, my latest upgraded design

Thanks. On the RIS-660A-1 I can see the point of D11 and D12 but I do not understand the need for D1 thru D8 ?

piglet

Right. I was going to pose that as a quiz question. Anybody have a comment?

Looks reasonable. Of course the slope of the response curve still depends on the beam diameter, which tends to be poorly controlled, and on small artifacts such as ghost reflections, scatter, and etalon fringes, so that extreme electronic precision is usually unnecessary.

I generally just measure the difference between the open-circuit voltages to get the log ratio from split cells--I have a nice box on my shelf that has a germanium quad cell, a dual op amp, and two edge-reading zero-centre meters arranged in X and Y. The quad cell is nicely centred in a 30-mm aluminum cylinder for use with rod-and-cage optomechanical systems such as Microbench. I've been using it for beam alignment for 27 years now. ;)

If I really needed the ratio, I'd use a ratio-only noise canceller with an on-chip-ovenized MAT14, and hack up the result in software to get the true ratio. It's a whole lot quieter than a divider. Laser noise tends to be spatially-dependent, due to vestigial side modes and spontaneous emission, so the quietness may not matter as much when you're putting a step discontinuity in the middle of the beam.

It's tougher to get the straight currents that way, of course, unless you use diodes with separate dice rather than CA or CC. (Photodiodes are usually made on N-type substrates--apparently illuminating through a P-type epi improves linearity, even if it increases the series resistance.)

Cheers

Phil Hobbs

OK are D11 and D12 for input protection on the opamp? (I don't know the LT1792) Are the others for some transient over voltage when the analog switch changes?

George H.

It took me a bit to see that Q1 was a ~10 V cap multiplier. Why the few extra resistors (R11 and R12)? I guess R12 keeps some minimum current flowing... is that less noise?

Re: PCB, Through hole, George like :^) When I did an early photodiode thing I ended up sanding off the ground plane under the TIA and switch section. (The less C the better... speed-wise.) So why a ground plane under the one section for which I would banish it?

Of course if you don't care about speed it doesn't matter.

George H. Oh and thanks for sharing!

That's a nV-level en noise we're seeking, so we want a few mA through the transistor. If the external PD connection is shorted, we want to limit the current and dissipate power in a collector resistor. A small emitter resistor isolates load capacitance, prevents oscillation.

Right. This application has 100pF of node capacitance, and runs at low speed, so we can indulge in a bit of shielding. Other faster designs have the nodes cleared out.

I think I missed it earlier - but now I see that the MUX Vee is -1V so I suppose those clamps are actually a good idea!

Was that the quiz right answer?

piglet

JT is always railing about how relying on substrate- diode conduction being bad engineering practice, at least for linear circuits. I don't know if he makes the same argument for CMOS, but it's a dangerous idea to have some of the switch diodes conducting, up to 1mA, while expecting others to behave themselves at the pA level..

My preference would be for a smaller emitter resistor, and a capacitor bypassing R17 (possibly resistor-capacitor in series, if power transient is an issue). The lower the impedance biasing the diodes, the less the crosstalk from the bias supply.

Wasting 20 mA in the bias supply won't burn anything up.

The emitter resistor keeps the transistor EF from oscillating at RF with a capacitive load.

I measured the hFE of a SN74HC02 at around 0.001. That's between the two input pins of one gate; there was no measurable effect on the other gate sections.

Not a worry for latchup, or ordinary logic duty (for most cases), but it would be a total killer in anything small signal or microcurrent!

Tim

Oops; my bad, I misread '33.2' as '33k'...

Whoa! I wonder what the mechanism was. What was your test current?

Same as any bipolar transistor: charge diffusion, of course! The ESD diodes are close enough together (10s of um?) that a very small amount of charge gets between them.

I even forget if I was biasing the high or low side diodes, and which one(s) were acting as collector, that I was measuring current from...

Probably, the high side diodes are safer to (ab)use, because they're in N-wells. So, the current mostly gets shunted to substrate, and any leakage between diodes would have to travel through four PN junctions. You might see it under latchup conditions, but, so what, you'll see stray currents

So, I was probably testing the low side diodes: pulling current out of one pin, and watching current into the other.

Test current was in the mA range, and I think leakage was more or less proportional to it. I don't have a sub-uA meter handy, so the measurement was crude.

They warn you about these sorts of things, from time to time (more often in analog bits like op-amps and switches). Now you know why. :)

Aside: want to hear another Remarkable Feat of Semiconduction? How about Widlar's riddle: how do you get negative voltage out of a single BJT, under static conditions? ;-)

Tim