Can some one tell me how to calculate the number of synchronizer stages when I want to transfer a signal from clk domain A to clk domain B...?
- posted
18 years ago
regarding synchronizer design
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- posted
18 years ago
The driving consideration, if you try to engineer the solution, will be how often metastability causes an output error from the synchronizer. This has been treated theoretically quite a bit. I suggest you do a web search on the words: metastability probability synchronizer. Here is a link:
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Of the hits that show up early, at least this one looks good:
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- posted
18 years ago
Two.
John
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- posted
18 years ago
If the signal changes state at the clock edge of the receiving system, that's OK; a 1 or a 0 is just as good when it was changing anyhow. The usual concern here is metastability.
John
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- posted
18 years ago
formatting link
You must be getting tired? Posting a simple Google link rather than cut-and-paste'ing the concepts, crudely, and representing them as your own, as you've done numerous times in the past...Good boy, poser.
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- posted
18 years ago
Or perhaps zero if you don't mind the glitches when the signal changes state at just the wrong time.
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- posted
18 years ago
In article , John Larkin wrote: [...]
metastability == glitches in this case. You get a glitch just after the clock edge when the metastabiltity happens. If the rest of the circuit doesn't care about the glitch, you can just ignore the problem.
-- -- kensmith@rahul.net forging knowledge