I tired of the TURD-TARD's vileness and turned the filters back on.
It's hard to believe that some coworker hasn't bludgeoned him to death by now.
If you hit a turd, it just splatters.
From his posting times I think he's night-shift janitor ;-)
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at
At the sewage treatment plant. That's why he never runs out of crap.
He must be the low man on the totem pole to have such contempt for all of USENET.
Must be why your posts appear in more than one group.
"Sewer treatment" is what occurs when I call retards like you what you are... a total piece of s*it.
Yeah, he's the part of the pole they stick in the ground to hold up the rest.
If that were true, you would be in a lot more pain.
Oh yeah... I know that one was miles over your head, as well as several others here.
Looks like this subject can get quite technical:
To effectively use copper pours for warpage prevention, follow these layout guidelines:
Symmetrical Stackups: Mirror your layer stackup and copper density from the center core outward. If Layer 2 has a heavy pour, Layer 3 should ideally have a matching copper density.Target 50-70% Coverage: Aim for a consistent copper density across all layers. Use your EDA software to calculate density percentages and try to keep layer-to-layer variance within 10-15%.
Use Cross-Hatched Pours: For flex circuits or thin substrates, choose a hatched (grid) pattern instead of a solid pour. Hatched copper relieves structural stress while allowing gaseous venting and better resin bonding during lamination.
Implement Copper Thieving: If a certain region of the board lacks circuitry, add "thieving" (isolated dots or grids of dummy copper) to balance the area density without altering the electrical net connections.
(I didn't know PCB EDA would compute % coverage of copper for any layer.)
Then:
If you are currently experiencing board warpage, let me know:
Is this a multilayer, double-sided, or single-sided board?
What is the total thickness of the PCB?
At what stage is the warping happening (fabrication or reflow soldering)?
I can help you pinpoint the exact cause and adjust your design rules to fix it.
-Google AI
Who needs USENET and a bunch of guesswork when AI can nearly instantly summarize the wisdom of an entire industry, representing millions of man-hours real experience. The world is changing at warp speed. Out with the old and in with new, whether anyone likes it or not.
Sometimes AI is wrong, and it doesn't know what I'm designing.
We have a board flatness spec on our fab drawings. We kinda try to keep the stack symmetric but it's sometimes not possible.
We seldom do 2-side boards. Most are 4 or 6 with an occasional 8, 10, and even one 12. Always an even number.
The usual 6-layer stack is
1 parts, signals, silk 2 solid ground 3 signals 4 signals 5 power pours, max coverage, no hatch 6 signals, sometimes parts with silkMost all our boards are about 0.062" thick or so.
One of my guys designed an 8-layer board, 9.5 x 13", with 2oz internals. It cost $620.
I haven't heard complaints from manufacturing about warpage. We have a newish Yamaha p+p. I bolt boards down to the chassis often, so a little warpage doesn't matter except as it might affect p+p.
This used different dielectrics on different layers.
John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics
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