Re: Job Description

This RFQ just crossed my desk...

> >"... CAD experience in automating analog IC design, analog IC design >(not physical) verification and analog IC test-benches regression. It >is a relatively new field in analog IC design, so it is not common. >Finding the right candidate will not be easy. However, if you ask the >candidate, he/she will tell you whether they have the experience >and/or interest." > >What really cracked me up was the "regression" thingy ;-) > >I guess that there is a class of village idiots out there who think >analog can be made VHDL-like... Bwahahahahahahaha ;-) > > ...Jim Thompson

I've been waiting for somebody, likely academics, to promote language-based analog IC and PC board design, using a behavioral description (as opposed to structural) language. I'm betting it will be an object-oriented C++ sort of thing.

Wasn't an analog flavor of VHDL proposed?

John

Reply to
John Larkin
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Yes, VHDL-AMS

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It's alive and well at least in terms of being able to get *simulators* for it, but I've never heard of any commercial *synthesis* tools for it... although you do see the occasional academic paper on the topic (e.g., eprints.ecs.soton.ac.uk/10645/1/Hamid_Kazmierski_Kluwer_2002.pdf ). The Verilog guys have their only deal, Verilog-A/AMS:
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.

Even without synthesis tools, VHDL-AMS and Verilog-AMS are useful in that you can build fancy testbenchs meant to test out "real" (physical) analog circuits that get simulated in SPICE or similar. I.e., it is entirely viable (and this is done commercially AFAIK) to build a testbench in *-AMS, start working on the actual circuit, verify it works with your somewhat idealized models, go through layout, extract an LVS model, and verify that with the added parasitics and coupling the design is still working.

---Joel

Reply to
Joel Koltner

If you're building juvenile-level System-on-Chip stuff, a descriptive language will do.

If you are in my boat, where performance AND power consumption must be optimized, it's a different game altogether.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
         America: Land of the Free, Because of the Brave
Reply to
Jim Thompson

So you're saying it's a method to develop a simulation test-bench, for an otherwise designed circuit?

I guess I sort of do that in situ ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
         America: Land of the Free, Because of the Brave
Reply to
Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

It's my understanding that if you're looking for real-world commercial applications of VHDL/Verilog-AMS (rather than just academic/research usage), yeah, that's where you find it: Implementing test benches for a circuit you (or your cohorts) designed using the traditional schematic entry/SPICE simulation/Cadence (or whoever) layout approach.

Yeah, but you're also using lots of fancy PSpice macros to test/measure your circuits as well, right? So I think you are doing a lot of the same things that the *-AMS guys are, just using different tools for it.

---Joel

Reply to
Joel Koltner

Yes. That was my conclusion also. I do indeed have many pages of PSpice macros... after all, my goal is to demonstrate to the end-customer that my design has met their specifications. There's nothing quite like a macro that shows results in the customer's terminology, rather than in some obscure current or voltage evaluation.

It's just the EDA types trying to snow the ignorant management types that decide on which EDA tools to buy ;-(

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
         America: Land of the Free, Because of the Brave
Reply to
Jim Thompson

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

There certainly is an element to that, although you'll also find a push from the academic and Big Standards guys: While PSpice does macros one way and SI-Metrix does them another way and HSpice does them a third way etc., etc.,

*if* one could come up with a decent testing/macro langauge, pretty much everyone stands to benefit if then all the simulator vendors are willing to "plug in" to that standard language.

As with any "standard," it's a very big "if..."

I think the mistake many managers make is overestimating how much any given software tool contributes to their success and underestimating how much their employees' talents do. Software vendors of course have a vested interest in encouraging this belief... (I suppose this is just another way of stating the same thing you wrote up there...)

---Joel

Reply to
Joel Koltner

[snip]

The problem is that there are NO standards.

Every committee attempt at universality, for instance EDIF, is a failure, because none of the participants actually want it to work... it's not to their benefit for me to be able to ship PSpice Schematics directly into Cadence Virtuoso.

That would mean we actually had competition.

For Cadence,"competition" means buy them out and kill their product.

If there was ever a "There ought to be a law"... :-(

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
         America: Land of the Free, Because of the Brave
Reply to
Jim Thompson

There are a lot of those, including an IQ test before being allowed online. They could call it "Dimmie's Law"

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Reply to
Michael A. Terrell

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Sure does.

One of the reasons we ended up with (AWR's) Microwave Office rather than, e.g., ADS or Ansoft Designer is because I was convinced that AWR's claim of being the "most open" (in terms of being able to interface to various EM solvers -- including their competitors' -- and being scriptable from anywhere via COM, e.g., you can script MWO from Excel if you feel like it...) were correct. Granted, this may have been motivated by their being a newcomer and wanting to gain market share, but they're made such a big deal of it for years now I can't imagine they'd ever be able to "close the doors" at this point.

OpenOffice has done a lot for making people think a little more about the somewhat closed system with an almost requisite regular payout (upgrade fees) they're getting into when they buy into Microsoft Office, I think.

---Joel

Reply to
Joel Koltner

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