Without doubt, it's the trickiest aspect of the design. Definitely do-able though. Let us know how you get on.
Without doubt, it's the trickiest aspect of the design. Definitely do-able though. Let us know how you get on.
"Cursitor Doom" snipped-for-privacy@notformail.com wrote in message news:veuirv$3cmo3$ snipped-for-privacy@dont-email.me...
...
Ok. This simple circuit is based on the circuit you can find here.
Version 4 SHEET 1 2196 916 WIRE -160 -160 -256 -160 WIRE -16 -160 -160 -160 WIRE 160 -160 -16 -160 WIRE 400 -160 224 -160 WIRE -160 -144 -160 -160 WIRE -256 -128 -256 -160 WIRE 400 -128 400 -160 WIRE -16 -80 -16 -160 WIRE -256 -32 -256 -64 WIRE -160 -32 -160 -64 WIRE -160 -32 -256 -32 WIRE -48 -32 -160 -32 WIRE 112 -32 48 -32 WIRE 208 -32 192 -32 WIRE 272 -32 208 -32 WIRE 400 -32 400 -48 WIRE 400 -32 352 -32 WIRE -352 32 -480 32 WIRE 128 32 -352 32 WIRE 208 64 208 -32 WIRE 208 64 48 64 WIRE -480 80 -480 32 WIRE 128 96 128 32 WIRE -352 112 -352 32 WIRE 48 112 48 64 WIRE 96 112 48 112 WIRE 384 128 160 128 WIRE 400 128 400 -32 WIRE 400 128 384 128 WIRE 480 128 400 128 WIRE 544 128 480 128 WIRE 96 144 -80 144 WIRE -80 224 -80 144 WIRE 16 224 -80 224 WIRE 176 224 16 224 WIRE 256 224 240 224 WIRE 384 224 384 128 WIRE 384 224 336 224 WIRE -80 240 -80 224 WIRE 16 240 16 224 WIRE -480 320 -480 160 WIRE -480 320 -560 320 WIRE -560 336 -560 320 WIRE -480 336 -480 320 WIRE -352 336 -352 176 WIRE -352 336 -480 336 WIRE -336 336 -352 336 WIRE -256 336 -256 -32 WIRE -256 336 -336 336 WIRE -80 336 -80 320 WIRE -80 336 -256 336 WIRE 16 336 16 304 WIRE 16 336 -80 336 WIRE -480 464 -480 336 WIRE -336 496 -336 336 WIRE -480 656 -480 544 WIRE -336 656 -336 560 WIRE -336 656 -480 656 WIRE 128 656 128 160 WIRE 128 656 -336 656 FLAG 480 128 output FLAG -560 336 0 DATAFLAG -432 32 "round(($)*100)/100" DATAFLAG 64 -32 "round(($)*100)/100" DATAFLAG 240 -32 "round(($)*100)/100" DATAFLAG 64 -160 "round(($)*100)/100" DATAFLAG 288 -160 "round(($)*100)/100" SYMBOL voltage -480 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL res 352 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 12k SYMBOL cap 240 208 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 15n SYMBOL cap 32 304 R180 WINDOW 0 -33 54 Left 2 WINDOW 3 -49 18 Left 2 SYMATTR InstName C2 SYMATTR Value 15n SYMBOL polcap -368 112 R0 SYMATTR InstName C4 SYMATTR Value 100µ SYMBOL OpAmps\\LT1057 128 64 R0 SYMATTR InstName U2 SYMBOL res -176 -160 R0 SYMATTR InstName R6 SYMATTR Value 47k SYMBOL res 208 -48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 4.7k SYMBOL res 368 -48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 13k SYMBOL diode 160 -144 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL res 384 -144 R0 SYMATTR InstName R9 SYMATTR Value 4.7k SYMBOL njf 48 -80 R90 WINDOW 0 -38 17 VRight 2 WINDOW 3 -7 -47 VRight 2 SYMATTR InstName J1 SYMATTR Value 2N3819 SYMBOL voltage -480 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL polcap -352 496 R0 SYMATTR InstName C5 SYMATTR Value 100µ SYMBOL res -96 224 R0 SYMATTR InstName R2 SYMATTR Value 12k SYMBOL polcap -240 -64 R180 WINDOW 0 -35 53 Left 2 WINDOW 3 -47 17 Left 2 SYMATTR InstName C3 SYMATTR Value 10µ TEXT -464 352 Left 2 !.tran 10
In your simulation? I can't tell, I'm afraid. I don't have LTspice (or even Wine which Linux needs) installed on this laptop and I won't have access to anything that does have it until Monday. Sorry about that.
[Snip...]
You're hitting the flat portion of the Id vs. Vds curve around the top of the wave. In that region the dynamic resistance of the FET is very large, and therefore the gain of the opamp drops to about one. As a result, the positive tip of the output gets sort-of squashed.
There are probably ways to fix this, for example by feeding a portion of the output signal to the FET gate, but a quick attempt I made didn't work very well. This is why FETs aren't so great as gain setting elements.
Using a lightbulb --or more generally a PTC resistor-- for R7 is really hard to beat.
Jeroen Belleman
Yes. The key was that they are thermal in principle, and yield a pure resistance that responds too slowly to follow the 1 KHz signal being generated, and so cause no parametric waveform distortion.
Joe Gwinn
But tricky to Spice.
And a thermal device of course makes the amplitude temperature sensitive, especially when the heating goes directly as the square of the sine amplitude.
It would be better to have the native loop gain very close to 1.00 and give the AGC mechanism a small influence, like +- a few per cent maybe.
A mosfet would make a decent voltage-controlled gain element, with that small influence.
There are still analog multiplier chips around. Barely.
Ok thanks Jeroen.
It looks like the best approach for the gain control is either a filament or something like that used in the document Bill Sloman posted.
"john larkin" snipped-for-privacy@glen--canyon.com wrote in message news: snipped-for-privacy@4ax.com...
Attempting to reduce the gain control range of the FET seems to run into other issues which I've seen in other simulations. The lower amplitue parts of the signal produced by this ciruit look nice and clean. Now I just need a way to stop it generating an AM radio signal. Manual adjustment of R8 is likely to be needed in any real circuit.
Version 4 SHEET 1 2196 916 WIRE -160 -224 -256 -224 WIRE -16 -224 -160 -224 WIRE 160 -224 -16 -224 WIRE 400 -224 224 -224 WIRE -160 -208 -160 -224 WIRE -256 -192 -256 -224 WIRE 400 -192 400 -224 WIRE -16 -144 -16 -224 WIRE -256 -96 -256 -128 WIRE -160 -96 -160 -128 WIRE -160 -96 -256 -96 WIRE -80 -96 -160 -96 WIRE -48 -96 -80 -96 WIRE 80 -96 48 -96 WIRE 112 -96 80 -96 WIRE 208 -96 192 -96 WIRE 272 -96 208 -96 WIRE 400 -96 400 -112 WIRE 400 -96 352 -96 WIRE -80 -32 -80 -96 WIRE -48 -32 -80 -32 WIRE 80 -32 80 -96 WIRE 80 -32 32 -32 WIRE -352 32 -480 32 WIRE 128 32 -352 32 WIRE 208 64 208 -96 WIRE 208 64 48 64 WIRE -480 80 -480 32 WIRE 128 96 128 32 WIRE -352 112 -352 32 WIRE 48 112 48 64 WIRE 96 112 48 112 WIRE 384 128 160 128 WIRE 400 128 400 -96 WIRE 400 128 384 128 WIRE 528 128 400 128 WIRE 560 128 528 128 WIRE 96 144 -80 144 WIRE -80 224 -80 144 WIRE 16 224 -80 224 WIRE 176 224 16 224 WIRE 256 224 240 224 WIRE 384 224 384 128 WIRE 384 224 336 224 WIRE -80 240 -80 224 WIRE 16 240 16 224 WIRE -480 320 -480 160 WIRE -480 320 -560 320 WIRE -560 336 -560 320 WIRE -480 336 -480 320 WIRE -352 336 -352 176 WIRE -352 336 -480 336 WIRE -336 336 -352 336 WIRE -256 336 -256 -96 WIRE -256 336 -336 336 WIRE -80 336 -80 320 WIRE -80 336 -256 336 WIRE 16 336 16 304 WIRE 16 336 -80 336 WIRE -480 464 -480 336 WIRE -336 496 -336 336 WIRE -480 656 -480 544 WIRE -336 656 -336 560 WIRE -336 656 -480 656 WIRE 128 656 128 160 WIRE 128 656 -336 656 FLAG 528 128 output FLAG -560 336 0 DATAFLAG -432 32 "round(($)*100)/100" DATAFLAG 64 -96 "round(($)*100)/100" DATAFLAG 240 -96 "round(($)*100)/100" DATAFLAG 64 -224 "round(($)*100)/100" DATAFLAG 288 -224 "round(($)*100)/100" SYMBOL voltage -480 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL res 352 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 12k SYMBOL cap 240 208 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 15n SYMBOL cap 32 304 R180 WINDOW 0 -33 54 Left 2 WINDOW 3 -49 18 Left 2 SYMATTR InstName C2 SYMATTR Value 15n SYMBOL polcap -368 112 R0 SYMATTR InstName C4 SYMATTR Value 100µ SYMBOL OpAmps\\LT1057 128 64 R0 SYMATTR InstName U2 SYMBOL res -176 -224 R0 SYMATTR InstName R6 SYMATTR Value 47k SYMBOL res 208 -112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 4.7k SYMBOL res 368 -112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 11500 SYMBOL diode 160 -208 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL res 384 -208 R0 SYMATTR InstName R9 SYMATTR Value 10k SYMBOL njf 48 -144 R90 WINDOW 0 -38 17 VRight 2 WINDOW 3 -7 -47 VRight 2 SYMATTR InstName J1 SYMATTR Value 2N3819 SYMBOL voltage -480 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL polcap -352 496 R0 SYMATTR InstName C5 SYMATTR Value 100µ SYMBOL res -96 224 R0 SYMATTR InstName R2 SYMATTR Value 12k SYMBOL polcap -240 -128 R180 WINDOW 0 -35 53 Left 2 WINDOW 3 -47 17 Left 2 SYMATTR InstName C3 SYMATTR Value 10µ SYMBOL res 48 -48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 1.5K TEXT -464 352 Left 2 !.tran 5
Note that the LDR has a very small influence range on the loop gain.
"john larkin" snipped-for-privacy@gct.com wrote in message news: snipped-for-privacy@4ax.com...
That's why I added R3 in this circuit. It does not seem to be safe to reduce R3 below 1k.
R4 helps a lot too for reasons I don't fully understand. It may be moving the FET to a better part of its operating characteristics.
A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V. As expected, this produces twice the output voltage and I've not found a way to reduce it.
This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using light dependent resistors. From the LTSpice plot, I can't discern any impurity in the signal this circuit produces. It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.
I haven't used an LDR since playing with an ORP12 around age 10. I seem to remember that they can degrade over time but maybe that only happens in sunlight.
Version 4 SHEET 1 2196 916 WIRE -160 -304 -256 -304 WIRE -16 -304 -160 -304 WIRE 160 -304 -16 -304 WIRE 400 -304 224 -304 WIRE -160 -272 -160 -304 WIRE 400 -272 400 -304 WIRE -256 -256 -256 -304 WIRE -16 -208 -16 -304 WIRE -256 -160 -256 -192 WIRE -256 -160 -288 -160 WIRE -160 -160 -160 -192 WIRE -160 -160 -256 -160 WIRE -80 -160 -160 -160 WIRE -48 -160 -80 -160 WIRE 80 -160 48 -160 WIRE 112 -160 80 -160 WIRE 208 -160 192 -160 WIRE 272 -160 208 -160 WIRE 400 -160 400 -192 WIRE 400 -160 352 -160 WIRE -288 -112 -288 -160 WIRE -80 -96 -80 -160 WIRE -48 -96 -80 -96 WIRE 80 -96 80 -160 WIRE 80 -96 32 -96 WIRE 208 -48 208 -160 WIRE 208 -48 48 -48 WIRE 272 -48 208 -48 WIRE 400 -48 400 -160 WIRE 400 -48 352 -48 WIRE -384 32 -512 32 WIRE 128 32 -384 32 WIRE -512 80 -512 32 WIRE 128 96 128 32 WIRE -384 112 -384 32 WIRE 48 112 48 -48 WIRE 96 112 48 112 WIRE 384 128 160 128 WIRE 400 128 400 -48 WIRE 400 128 384 128 WIRE 528 128 400 128 WIRE 560 128 528 128 WIRE 96 144 -80 144 WIRE -80 224 -80 144 WIRE 16 224 -80 224 WIRE 176 224 16 224 WIRE 256 224 240 224 WIRE 384 224 384 128 WIRE 384 224 336 224 WIRE -80 240 -80 224 WIRE 16 240 16 224 WIRE -512 320 -512 160 WIRE -512 320 -592 320 WIRE -592 336 -592 320 WIRE -512 336 -512 320 WIRE -384 336 -384 176 WIRE -384 336 -512 336 WIRE -368 336 -384 336 WIRE -288 336 -288 -32 WIRE -288 336 -368 336 WIRE -80 336 -80 320 WIRE -80 336 -288 336 WIRE 16 336 16 304 WIRE 16 336 -80 336 WIRE -512 464 -512 336 WIRE -368 496 -368 336 WIRE -512 656 -512 544 WIRE -368 656 -368 560 WIRE -368 656 -512 656 WIRE 128 656 128 160 WIRE 128 656 -368 656 FLAG 528 128 output FLAG -592 336 0 DATAFLAG -464 32 "round(($)*100)/100" DATAFLAG 64 -160 "round(($)*100)/100" DATAFLAG 240 -160 "round(($)*100)/100" DATAFLAG 64 -304 "round(($)*100)/100" DATAFLAG 288 -304 "round(($)*100)/100" SYMBOL voltage -512 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL res 352 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL cap 240 208 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 15n SYMBOL cap 32 304 R180 WINDOW 0 -33 54 Left 2 WINDOW 3 -49 18 Left 2 SYMATTR InstName C2 SYMATTR Value 15n SYMBOL polcap -400 112 R0 SYMATTR InstName C4 SYMATTR Value 100µ SYMBOL OpAmps\\LT1057 128 64 R0 SYMATTR InstName U2 SYMBOL res -176 -288 R0 SYMATTR InstName R6 SYMATTR Value 47k SYMBOL res 208 -176 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 4.7k SYMBOL res 368 -176 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 12k SYMBOL diode 160 -288 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL res 384 -288 R0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL njf 48 -208 R90 WINDOW 0 -39 17 VRight 2 WINDOW 3 -10 -13 VRight 2 SYMATTR InstName J1 SYMATTR Value J112 SYMBOL voltage -512 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL polcap -384 496 R0 SYMATTR InstName C5 SYMATTR Value 100µ SYMBOL res -96 224 R0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL polcap -240 -192 R180 WINDOW 0 -35 53 Left 2 WINDOW 3 -47 17 Left 2 SYMATTR InstName C3 SYMATTR Value 10µ SYMBOL res 48 -112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -272 -16 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R4 SYMATTR Value 150 SYMBOL res 368 -64 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 270k TEXT -496 352 Left 2 !.tran 3 TEXT -536 -392 Left 2 ;Edward Rawde's 1KHz sinewave oscillator. 18 Oct 2024.\nCan the sine purity be inproved any further?
LDRs are awful. Drifty, nonlinear, bad frequency response. But with a small influence, inside a tight control loop, they will work.
I got your earlier circuit to work a lot better simply by increasing R7 to 5.6k. If you use the View option on the trace viewing panel to pull out an FFT of the output (I use Blackmann-Harris windowing) from 10sec to 20 sec, you can see that second harmonic distortion is about 20dB below the primary - not great but better than it was.
And the waveform looks like a sine wave.
The less influence the FET has on the gain of the circuit, the better the sine wave.
The AD734 would do a lot better - or at least it does in my simulations
- but it isn't cheap.
emiconductors.
If all the components are perfect and correctly matched.
In a practical oscillator where the resistors are switched or the capacitors ganged, there will be slight mis-matches due to tolerances and the loss will be greater (and unpredictable).
The whole point about Wein bridges is that they are perfectly linear.
You have to introduce a controllable non-linearity that lets you tweak the gain to be exactly three when they are oscillating at the right amplitude, and dial it back if the amplitude is too big, or dial it up if it is too low.
In practice tolerance on the two crucial capacitors and resistors means that the gain for stable output is never going to be exactly three.
Just for kicks I simulated one with a thirty degree phase shift in the RC pairs (rather than the classical forty five degree phase shift) and it worked fine too.
Clipper's add harmonic content. Multipliers can do better. The AD734 adds some harmonic content but it can be 70dB below the fundamental, and if the tweak you need is 50dD below the main signal path, your op amp will add as much.
Sigma-delta DACs do rely on pulse width modulation. A well-designed Wein bridge can keep the harmonic content of the output
120dD below the fundamental, and DDS devices can't do that without heavy filtering of the output.Cheap digital junk doesn't blow away a well-designed Wein bridge. It may blow away anything that John Larkin can design, but that's a different competition.
"Bill Sloman" snipped-for-privacy@ieee.org wrote in message news:vevqip$3q3dn$ snipped-for-privacy@dont-email.me...
If you run this circuit then View, FFT, Use current zoom extent, Ok It implies that unwanted harmonics are 40dB down. I'm not sure I believe that but if true then it's not bad for a very low cost circuit.
Version 4 SHEET 1 2196 916 WIRE -160 -304 -256 -304 WIRE -16 -304 -160 -304 WIRE 96 -304 -16 -304 WIRE 160 -304 96 -304 WIRE 400 -304 224 -304 WIRE -160 -272 -160 -304 WIRE 96 -272 96 -304 WIRE 400 -272 400 -304 WIRE -256 -256 -256 -304 WIRE -16 -208 -16 -304 WIRE -256 -160 -256 -192 WIRE -256 -160 -288 -160 WIRE -160 -160 -160 -192 WIRE -160 -160 -256 -160 WIRE -80 -160 -160 -160 WIRE -48 -160 -80 -160 WIRE 80 -160 48 -160 WIRE 96 -160 96 -192 WIRE 96 -160 80 -160 WIRE 112 -160 96 -160 WIRE 208 -160 192 -160 WIRE 272 -160 208 -160 WIRE 400 -160 400 -192 WIRE 400 -160 352 -160 WIRE -288 -112 -288 -160 WIRE -80 -96 -80 -160 WIRE -48 -96 -80 -96 WIRE 80 -96 80 -160 WIRE 80 -96 32 -96 WIRE 208 -48 208 -160 WIRE 208 -48 48 -48 WIRE 272 -48 208 -48 WIRE 400 -48 400 -160 WIRE 400 -48 352 -48 WIRE -384 32 -512 32 WIRE 128 32 -384 32 WIRE -512 80 -512 32 WIRE 128 96 128 32 WIRE -384 112 -384 32 WIRE 48 112 48 -48 WIRE 96 112 48 112 WIRE 384 128 160 128 WIRE 400 128 400 -48 WIRE 400 128 384 128 WIRE 528 128 400 128 WIRE 608 128 528 128 WIRE 96 144 -80 144 WIRE -80 208 -80 144 WIRE -80 208 -176 208 WIRE -80 224 -80 208 WIRE 16 224 -80 224 WIRE 176 224 16 224 WIRE 256 224 240 224 WIRE 384 224 384 128 WIRE 384 224 336 224 WIRE -176 240 -176 208 WIRE -80 240 -80 224 WIRE 16 240 16 224 WIRE -512 320 -512 160 WIRE -512 320 -592 320 WIRE -592 336 -592 320 WIRE -512 336 -512 320 WIRE -384 336 -384 176 WIRE -384 336 -512 336 WIRE -368 336 -384 336 WIRE -288 336 -288 -32 WIRE -288 336 -368 336 WIRE -176 336 -176 320 WIRE -176 336 -288 336 WIRE -80 336 -80 320 WIRE -80 336 -176 336 WIRE 16 336 16 304 WIRE 16 336 -80 336 WIRE -512 464 -512 336 WIRE -368 496 -368 336 WIRE -512 656 -512 544 WIRE -368 656 -368 560 WIRE -368 656 -512 656 WIRE 128 656 128 160 WIRE 128 656 -368 656 FLAG 528 128 output FLAG -592 336 0 DATAFLAG -464 32 "round(($)*100)/100" DATAFLAG 64 -160 "round(($)*100)/100" DATAFLAG 240 -160 "round(($)*100)/100" DATAFLAG 64 -304 "round(($)*100)/100" DATAFLAG 288 -304 "round(($)*100)/100" SYMBOL voltage -512 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL res 352 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL cap 240 208 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 15n SYMBOL cap 32 304 R180 WINDOW 0 -33 54 Left 2 WINDOW 3 -49 18 Left 2 SYMATTR InstName C2 SYMATTR Value 15n SYMBOL polcap -400 112 R0 SYMATTR InstName C4 SYMATTR Value 100µ SYMBOL OpAmps\\LT1057 128 64 R0 SYMATTR InstName U2 SYMBOL res -176 -288 R0 SYMATTR InstName R6 SYMATTR Value 47k SYMBOL res 208 -176 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 4.7k SYMBOL res 368 -176 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 12k SYMBOL diode 160 -288 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL res 384 -288 R0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL njf 48 -208 R90 WINDOW 0 -39 17 VRight 2 WINDOW 3 -10 -13 VRight 2 SYMATTR InstName J1 SYMATTR Value J112 SYMBOL voltage -512 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 10 135 Left 2 WINDOW 0 12 7 Left 2 WINDOW 3 15 104 Left 2 SYMATTR SpiceLine Rser=0.1 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL polcap -384 496 R0 SYMATTR InstName C5 SYMATTR Value 100µ SYMBOL res -96 224 R0 SYMATTR InstName R2 SYMATTR Value 12k SYMBOL polcap -240 -192 R180 WINDOW 0 -35 53 Left 2 WINDOW 3 -47 17 Left 2 SYMATTR InstName C3 SYMATTR Value 10µ SYMBOL res 48 -112 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -272 -16 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R4 SYMATTR Value 180 SYMBOL res 368 -64 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 270k SYMBOL res 80 -288 R0 WINDOW 0 36 43 Left 2 WINDOW 3 36 65 Left 2 SYMATTR InstName R10 SYMATTR Value 150k SYMBOL res -192 224 R0 SYMATTR InstName R11 SYMATTR Value 100k TEXT -496 352 Left 2 !.tran 0 3 2.5 TEXT -536 -392 Left 2 ;Edward Rawde's 1KHz sinewave oscillator. 19 Oct 2024.\nCan the sine purity be improved any further?
On 18/10/2024 4:46 pm, john larkin wrote:
Here is an amusing oscillator that has a voltage follower as the active stage - it has no voltage gain so some people say it cannot work - they are wrong of course.
Amplitude grows to power rail limits and non-linearities creep in.
Version 4 SHEET 1 1132 680 WIRE 640 -272 400 -272 WIRE 784 -272 640 -272 WIRE 928 -272 784 -272 WIRE 1072 -272 928 -272 WIRE 640 -224 640 -272 WIRE 400 -144 400 -272 WIRE 784 -144 784 -272 WIRE 640 -96 640 -144 WIRE 720 -96 640 -96 WIRE 640 -64 640 -96 WIRE 928 -48 928 -272 WIRE 1072 -48 1072 -272 WIRE 272 -16 64 -16 WIRE 400 -16 400 -64 WIRE 400 -16 336 -16 WIRE 432 -16 400 -16 WIRE 576 -16 432 -16 WIRE 784 0 784 -48 WIRE 864 0 784 0 WIRE 432 32 432 -16 WIRE 784 48 784 0 WIRE 64 96 64 -16 WIRE 160 96 64 96 WIRE 304 96 240 96 WIRE 1072 112 1072 32 WIRE 64 128 64 96 WIRE 432 160 432 112 WIRE 784 176 784 128 WIRE 64 224 64 192 WIRE 160 224 64 224 WIRE 304 224 304 96 WIRE 304 224 240 224 WIRE 640 224 640 32 WIRE 880 224 640 224 WIRE 928 224 928 48 WIRE 928 224 880 224 WIRE 64 256 64 224 WIRE 928 304 928 224 WIRE 64 352 64 320 WIRE 160 352 64 352 WIRE 304 352 304 224 WIRE 304 352 240 352 WIRE 640 352 640 224 WIRE 640 352 304 352 WIRE 64 384 64 352 WIRE 928 464 928 384 WIRE 64 480 64 448 FLAG 432 160 0 FLAG 928 464 0 FLAG 64 480 0 FLAG 1072 112 0 FLAG 784 176 0 FLAG 880 224 OUT SYMBOL res 256 368 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 470 SYMBOL res 256 240 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R2 SYMATTR Value 4700 SYMBOL res 256 112 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 47k SYMBOL cap 80 384 M0 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL cap 80 128 M0 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL cap 80 256 M0 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL npn 720 -144 R0 SYMATTR InstName Q2 SYMATTR Value 2N2222 SYMBOL voltage 1072 -64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 20 SYMBOL res 416 16 R0 SYMATTR InstName R5 SYMATTR Value 470k SYMBOL pnp 576 32 M180 SYMATTR InstName Q1 SYMATTR Value 2N3906 SYMBOL npn 864 -48 R0 SYMATTR InstName Q3 SYMATTR Value 2N2222 SYMBOL res 624 -240 R0 SYMATTR InstName R6 SYMATTR Value 220k SYMBOL res 768 32 R0 SYMATTR InstName R7 SYMATTR Value 4700 SYMBOL res 912 288 R0 SYMATTR InstName R8 SYMATTR Value 1000 SYMBOL res 384 -160 R0 SYMATTR InstName R4 SYMATTR Value 470k SYMBOL cap 336 -32 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 100n TEXT 728 480 Left 2 !.tran 100m TEXT 400 432 Left 2 ;EPW SED OCT 2024 TEXT 304 480 Left 2 ;VOLTAGE FOLLOWER RC OSC
piglet
On 18/10/2024 6:47 pm, Edward Rawde wrote:
Filaments, NTC thermistors and LDRs are awkward I agree. Sadly even JFETs are less mainstream than before. Here is an illustration I made showing a BJT long tail pair current steering the collector current of a basic ladder RC phase shift osc. Q1 is the oscillator and Q2-Q3 divert current into the load resistance as AGC directs.
Version 4 SHEET 1 1480 680 WIRE 352 -352 304 -352 WIRE 560 -352 352 -352 WIRE -608 -336 -608 -432 WIRE -496 -336 -496 -432 WIRE 304 -320 304 -352 WIRE 928 -272 928 -320 WIRE -128 -240 -128 -352 WIRE 0 -192 -64 -192 WIRE 112 -192 0 -192 WIRE 304 -192 304 -240 WIRE 304 -192 176 -192 WIRE 928 -176 928 -208 WIRE -608 -128 -608 -256 WIRE -496 -128 -496 -256 WIRE -352 -96 -368 -96 WIRE -128 -96 -128 -144 WIRE -128 -96 -352 -96 WIRE 304 -96 304 -192 WIRE 560 -96 560 -352 WIRE 0 -80 0 -192 WIRE 240 -48 144 -48 WIRE 672 -48 624 -48 WIRE 752 -48 672 -48 WIRE 800 -48 752 -48 WIRE 928 -48 928 -96 WIRE 928 -48 864 -48 WIRE -128 -32 -128 -96 WIRE 672 -16 672 -48 WIRE 752 -16 752 -48 WIRE 144 0 144 -48 WIRE 304 32 304 0 WIRE 432 32 304 32 WIRE 560 32 560 0 WIRE 560 32 432 32 WIRE 928 32 928 -48 WIRE 0 64 0 0 WIRE -608 112 -608 32 WIRE -496 112 -496 32 WIRE -128 112 -128 48 WIRE -128 128 -128 112 WIRE 144 128 144 80 WIRE 432 160 432 32 WIRE 672 160 672 64 WIRE 752 160 752 48 WIRE 928 160 928 96 WIRE -368 208 -368 -96 WIRE -256 208 -368 208 WIRE -128 208 -176 208 WIRE -80 208 -128 208 WIRE 64 208 0 208 WIRE 112 208 64 208 WIRE 240 208 192 208 WIRE 368 208 240 208 WIRE -608 240 -608 192 WIRE -496 240 -496 192 WIRE -128 288 -128 208 WIRE 64 288 64 208 WIRE 240 288 240 208 WIRE 432 304 432 256 WIRE 528 304 432 304 WIRE 528 320 528 304 WIRE 432 336 432 304 WIRE -128 368 -128 352 WIRE 64 368 64 352 WIRE 240 368 240 352 WIRE 528 416 528 384 WIRE 432 448 432 416 WIRE 528 528 528 496 FLAG -128 368 0 FLAG 64 368 0 FLAG 240 368 0 FLAG 528 528 0 FLAG -608 -128 0 FLAG 144 128 0 FLAG -608 240 0 FLAG -608 -432 P10 FLAG 352 -352 P10 FLAG -608 32 N10 FLAG 432 448 N10 FLAG -128 112 N10 FLAG -496 240 0 FLAG -496 32 N5 FLAG -496 -128 0 FLAG -496 -432 P5 FLAG 0 64 0 FLAG 928 160 0 FLAG 752 160 0 FLAG -352 -96 OUT FLAG 928 -320 OUT FLAG -128 -352 P10 FLAG 672 160 0 SYMBOL voltage -608 -352 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL npn 368 160 R0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL npn 240 -96 R0 SYMATTR InstName Q2 SYMATTR Value 2N3904 SYMBOL npn 624 -96 M0 SYMATTR InstName Q3 SYMATTR Value 2N3904 SYMBOL res 288 -336 R0 SYMATTR InstName R6 SYMATTR Value 22k SYMBOL res 416 320 R0 SYMATTR InstName R4 SYMATTR Value 22k SYMBOL res 208 192 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 47k SYMBOL res 16 192 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 47k SYMBOL res -160 192 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 47k SYMBOL cap -144 288 R0 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL cap 48 288 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL cap 224 288 R0 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL cap 512 320 R0 SYMATTR InstName C4 SYMATTR Value 0.01m SYMBOL npn -64 -240 M0 SYMATTR InstName Q4 SYMATTR Value 2N3904 SYMBOL res -112 -48 M0 SYMATTR InstName R10 SYMATTR Value 3300 SYMBOL cap 912 -272 R0 SYMATTR InstName C6 SYMATTR Value 100n SYMBOL res 512 400 R0 SYMATTR InstName R5 SYMATTR Value 100 SYMBOL voltage 144 -16 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V5 SYMATTR Value 1 SYMBOL voltage -608 96 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value -10 SYMBOL res 912 -192 R0 SYMATTR InstName R8 SYMATTR Value 100k SYMBOL res -16 -96 R0 SYMATTR InstName R9 SYMATTR Value 100k SYMBOL cap 112 -176 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C7 SYMATTR Value 1000n SYMBOL voltage -496 96 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value -5 SYMBOL voltage -496 -352 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL diode 864 -64 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D1 SYMATTR Value 1N914 SYMBOL diode 944 96 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D2 SYMATTR Value 1N914 SYMBOL cap 736 -16 R0 SYMATTR InstName C5 SYMATTR Value 1000n SYMBOL res 656 -32 R0 SYMATTR InstName R7 SYMATTR Value 470k TEXT -624 472 Left 2 !.tran 3000m startup TEXT 920 480 Left 2 ;EPW SED OCT 2024 TEXT 664 536 Left 2 ;CURRENT STEER AGC ON LADDER RC OSC
piglet
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If you move the ground to the emitter of Q3 and slide R8 through the power supply to the collector of Q3 you can see that it is a conventional phase shift oscillator with feedback from the output of an inverting amplifier via a 3-stage RC network.
kw
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