Double balanced diode mixer question

The LO isn't matched, or at least not by the mixer. To first order, the resistance of the diodes isn't a consideration. Ideally, their impedance is zero when forward biased and infinite when reverse biased.

The IF load is matched to the RF source, because the diodes connect those through to each other, with the polarity changing each half-period of the LO.

In practice, of course, the diodes have finite non- zero impedances, which cause losses and signal leakage between ports, both unwanted.

Jeroen Belleman

Am 05.12.18 um 12:06 schrieb snipped-for-privacy@gmail.com:

in particular (linked from there):

< >

A site full of treasures. Finally, a prof. who does not hide his stuff behind the IEEE paywall.

cheers, Gerhard

Are you using LT Spice? You could use one of the schottky diodes in its pull-down list. Some of them would be fine at 100 MHz.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

On 5.12.18 13:06, snipped-for-privacy@gmail.com wrote:

Your frequency selection is bad, with the signal a multiple of the oscillator frequency.

The diodes in a diode mixer are overdriven hard, to function as switches, and the load on oscillator input is highly non-linear. There will be no impedance match here, especially with a diode ring. You need a matching attenuator here, if the oscillator is fussy about its load.

To get useful output from the mixer, you do need a resonant circuit at the desired output frequency at the output, otherwise you'll see just a mess.

Here's a LTspice model of the Heathkit HW-101 balanced modulator, mixing from baseband audio to

3.3 MHz double-sideband signal:

Version 4 SHEET 1 1780 680 WIRE 752 112 608 112 WIRE 1008 112 752 112 WIRE 1200 112 1008 112 WIRE 1472 112 1360 112 WIRE 1600 112 1472 112 WIRE 608 144 608 112 WIRE 752 144 752 112 WIRE 1008 144 1008 112 WIRE 1200 224 1200 112 WIRE 1360 224 1360 112 WIRE 1472 240 1472 112 WIRE 96 272 32 272 WIRE 160 272 96 272 WIRE 352 272 240 272 WIRE 448 272 352 272 WIRE 608 272 608 208 WIRE 608 272 512 272 WIRE 656 272 608 272 WIRE 752 272 752 208 WIRE 752 272 720 272 WIRE 832 272 752 272 WIRE 1008 272 1008 224 WIRE 1008 272 912 272 WIRE 832 304 832 272 WIRE 1008 304 1008 272 WIRE 608 320 608 272 WIRE 752 320 752 272 WIRE 912 320 912 272 WIRE 96 336 96 272 WIRE 352 336 352 272 WIRE 608 432 608 384 WIRE 752 432 752 384 WIRE 752 432 608 432 WIRE 1008 432 1008 384 WIRE 1008 432 752 432 WIRE 1200 432 1200 304 WIRE 1200 432 1008 432 WIRE 1360 432 1360 304 WIRE 1472 432 1472 304 WIRE 1472 432 1360 432 WIRE 1472 464 1472 432 WIRE 96 480 96 416 WIRE 352 480 352 400 WIRE 912 480 912 384 WIRE 912 608 912 560 FLAG 96 480 0 FLAG 832 304 0 FLAG 912 608 0 FLAG 352 480 0 FLAG 1472 464 0 FLAG 1600 112 out IOPIN 1600 112 Out FLAG 32 272 in IOPIN 32 272 In SYMBOL voltage 96 320 R0 SYMATTR InstName V1 SYMATTR Value SINE(0 0.5 1k) SYMBOL voltage 912 464 R0 SYMATTR InstName V2 SYMATTR Value SINE(0 1.5 3.3Meg) SYMBOL res 256 256 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 2k SYMBOL cap 512 256 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1

SYMBOL cap 720 256 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL diode 624 208 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL diode 624 384 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL diode 736 144 R0 SYMATTR InstName D3 SYMATTR Value 1N4148 SYMBOL diode 736 320 R0 SYMATTR InstName D4 SYMATTR Value 1N4148 SYMBOL res 992 128 R0 SYMATTR InstName R2 SYMATTR Value 320 SYMBOL res 992 288 R0 SYMATTR InstName R3 SYMATTR Value 320 SYMBOL cap 896 320 R0 SYMATTR InstName C3 SYMATTR Value 100p SYMBOL ind2 1184 320 M180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L1

SYMATTR Type ind SYMBOL cap 336 336 R0 SYMATTR InstName C7 SYMATTR Value 40n SYMBOL ind2 1376 320 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L2

SYMATTR Type ind SYMBOL cap 1456 240 R0 SYMATTR InstName C5 SYMATTR Value 375p TEXT 104 568 Left 2 !.tran 0 10m 2m TEXT 1232 504 Left 2 !K L1 L2 0.5

--

-TV

+1 good observation m

Thank you very much for pointing out that the IF load and the RF source need to be matched.

Thank you very much for the helpful suggestions. However, the LTSpice netlist could not not be used, as I use HSpice(work) a nd Ngspice(home).

I did get a 35 MHz(local oscillator) and 100 MHz(RF) double balanced mixer to work. The output is analysed with a straightforward C language Disrete Fourier Transform orogram that I wrote sometine ago. The first three highest peaks in the power spectrum are:

3 highest frequencies and peaks 4.958516e+06 Hz 89.167763 6.451290e+07 Hz 68.324520 1.339843e+08 Hz 29.739029 Neither the LO(35 MHz) nor the RF(100.0MHz) show up in the highest 3 peaks. In fact, the third highest peak is at 133.9 MHz, which is very closes to the sum of the LO and RF frequencies(135 MHz). So, this design, though not optimum is working. the

Thank you very much for the link to a superb paper, whose author presents the topic in a clear straightforward way. You are right that the arxiv.org is a treasure tove of good papaers. Some years ago, I got hold of a similar good paper on the Zobel impedance matching network, and how it can be used to tackle any type of complex impedance matching case, for broadband applications.

In this mixer paper, I really like a line the author has put in the introduction. "However simple it seems, every time I try to explain the double balanced mixer to a colleague, something goes wrong".

[Snip! ...]

Cleaning up the results of your Fourier transform program, what you see is 5 MHz, 65 MHz and 135 MHz. The last two are (100-35)MHz and (100+35)MHz, the principal mixer products. The 5MHz is actually (100-3*35)MHz, the product of the RF with the 3rd harmonic of the LO. The LO is, or should be, driven hard, so it has the harmonics one expects of a square wave.

Jeroen Belleman

< >

Ahhmmm.... well I can't say I agree with the bit about (p.15)

if= Is .exp(vf/nVt)

with the comment that Is and n "is of limited usefulness ....as those parameters are hardly available...."

To the contrary, these are the most basic parameters of the spice diode model, readily available, and extremely useful.

The basic problem with the paper for me, is that it is like 30+ years out of date. Whilst it looks impressive to belt out huge equations involving modified Bessel functions and so forth, it is essentially, of no to little value. The reality is, fully practical and optimised design is only possible using software tools. Piddling about with ginormous equations is a complete waste of time. No one in the modern engineering world, does it, or if they do, shouldn't. They are way to large to manage. These university professors just haven't caught up to this real world. Possible because it puts them out of a job.

The reality is that today (last 20 years) all significant number analog/rf design is done in asics, using simulation tools. Period. By significant, I mean the billions of mobile phones built using asics.

All asic design is done, essentially, 99.999% using simulation. In practice, the vast number of engineers producing real designs, actually have quite limited knowledge of the theory described in that paper, yet achieves, successful real designs. This is because one only need to know the overall principles, and drive the tools that doactually know the details. For example, millions that use LTSpice, have no idea how spice works.

The tools just spit out all the correct non-linear analysis results. The task of the engineer is to intelligently run parameter sweeps, Monte Carlo and Worst Case runs. I suggest having a look at the Cadence web site to see the facilities in their tools, e.g. compression points, mixer gain, load pull, phase noise etc...all automated.

In fact I am aware of a specific result in phase noise, that to my knowledge, only became apparent and understood because of the tools. Manual calculation of phase noise, is literally, impossible, for real designs. Yet that does not stop one designing novel circuits in simulation with phase noise performance exceeding anything attempted by hand or by on the bench.

The world today is a computerised one. These proffs need to move on.

-- Kevin Aylward

- SuperSpice

Software tools are worthless unless one knows what to expect with a given input set. This was rightfully pointed out to me by my boss in Silicon Labs about five years ago.

In this case of an experimental double balanced mixer, I can believe the results because the power spectrum of the IF output has two promienent peaks at the two frequencies (f_RF - f_LO) and (f_RF + f_LO), as expected.

On the other I am sure one knows about Intel's classic blunder -- the Itanium microprocessor. It would be unwise to assume that Intel, with such vast resources at its disposal did not spend thousands of engineering hours in formal, timing etc., verification of the design. BUT Mother Nature had the last laugh. The Intel engineers, in their zeal to design and build the ultimate microprocessor by marrying CISC and RISC on the same chip did not consider heating effects -- they ignored physics.

The results are known to all. As soon as the first prototypes were tested, they went into thermal shutdown mode, within seconds. The Itanium was designed to power servers -- it would be exciting to have server that is working one second, and down the next. As one of my past profs(Dr. Jacob Abraham) at UT-Austin once remarked to one of his research students -- "that chip is not going to work, even if Intel pours in another billion dollars into it".

Sure, one needs to understand what they are doing. However, that has no baring on the fact that modern, practical, commercial design absolutely relies on simulation tools. Its the core way products are designed. Its simply *impossible* to design analog products with 100,000s of transistors on the bench, or using just pen and paper, or for that matter, digital products with billions of transistors.

I agree, and this might rattle a few... in my experience and opinion of interviewing ascic engineers, only 1%-2% were "competent", that is, have even the most basic understanding of matters such as how a band gap reference works, despite claiming 6 such designs on their CV, and 20 years of alleged experience. I have a one transistor BG test circuit I use, that only 1 in 50 pass. Its pretty stunning actually.

This is a different issue though, form the necessity of using simulation tools as fundamental to modern design.

Sure, one can miss things. Its extremely difficult to ensure that all relevant simulations have actually been done. However, 100,000s to millions of potential issues *do* get caught in simulations. Simulation can typically get a first time pass of extremely complicated analog asics that are typically ok for customer sampling, even if they do need a 2nd pass to tidy up a few details.

Typically, the errors are not that the simulation can't show them, but that even though 100,000s of simulations runs are done, some types of runs are simply missed. Sure, it requires knowledge and experience to use simulation tools effectively.

Sure, we all have stories where we made a less than "optimum" design decision. Humans make mistakes. That's reality. However, they make way fewer when computers are preventing the millions of other mistakes.

One of the key points I was making was concerning the academic based approach, i.e. highly complicated equations. These equations are simply useless for real design, and its just a fact than, essentially, no one uses them. One needs to appreciate that analytic solutions for 99.9999999999999% of all equations, are impossible. For example, look what's involved to solve just a transistor-resister circuit.

Design today, must be done from the framework of simulation. Understand the overall principles, well, qualitivity, and use the tools to do the details.

I am explaining what is actually done, as a matter of fact. Its what I do. Billions and billions of stars... err...I mean ASICs units are all designed entirely in the virtual world. A typical analog ASICs might have say, 100 main blocks, arranged in a hierarchy 10 deep with maybe 100,000 connections. Its the only practical way to design such systems

-- Kevin Aylward

- SuperSpice