PSpice and LTSpice

Post a sample. Shouldn't be any _significant_ difference... maybe polynomial versus behavioral ?? ...Jim Thompson

-- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

| 1962 | I love to cook with wine. Sometimes I even put it in the food.

"Jim Thompson" schreef in bericht news: snipped-for-privacy@4ax.com...

I add two listings that show the differences very clear.

The first is a listing of the circuit involved. A three pole Sallen-Key low pass filter. I need it to filter the harmonics from a PWM-based sinewave generator. So far I see too much remnants of the sample frequency - in the

19-20kHz range - on the o'scope. My LTSpice program does not recognize it.

The second you will recognize easily. It's a LTSpice listing of a very different circuit laying around here. Guess I got it from this NG.

• Netlist generated by ActiveLP

• --- Active Low-Pass Filter ----

• Filter Topologie: Sallen-Key

• Filter Type: Butterworth

• Filter Order: 3

• -3 dB-Frequency: 300 Hz V1 O0 0 AC 1 0 PULSE(0 1 0 33.333u 33.333u 33.333m)

• Ideal Circuit using Voltage controlled Voltage Sources RI1A O0 BI1 112.88 CI1A BI1 0 4.7u EI1 OI1 0 BI1 0 1 RI2A OI1 AI2 78.805 RI2B AI2 BI2 162.34 CI2A BI2 0 2.2u CI2B AI2 OI2 10u EI2 OI2 0 BI2 0 1 .graph OI2 curveLabel="Output Stage 2 Ideal" nowarn=true ylog=auto

• Simulation Control .TRAN 0 66.667m 0 33.333u .AC DEC 1k 3 3k

Version 4 SHEET 1 2100 1172 WIRE 848 -416 752 -416 WIRE 1040 -416 928 -416 WIRE 752 -304 752 -416 WIRE 848 -304 752 -304 WIRE 1040 -304 1040 -416 WIRE 1040 -304 912 -304 WIRE 1104 -304 1040 -304 WIRE 1152 -304 1104 -304 WIRE 752 -272 752 -304 WIRE 752 -160 752 -208 FLAG 752 -160 0 FLAG 1104 -304 out SYMBOL Digital\\schmtinv 848 -368 R0 WINDOW 3 30 111 Left 0 WINDOW 123 34 145 Left 0 SYMATTR InstName A1 SYMATTR Value vhigh=5 vlow=0 trise=25n SYMATTR Value2 tripdt=5n vt=2.5 vh=.9 SYMBOL cap 736 -272 R0 SYMATTR InstName C2 SYMATTR Value 100n ic=0 SYMBOL Misc\\EuropeanResistor 832 -400 R270 WINDOW 0 27 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName R1 SYMATTR Value 100k TEXT 536 -392 Left 0 !.tran 0 200m 0 uic

petrus bitbyter

If you are looking for compatibility between these two programs at the schematic level you will be sadly disappointed. You simply need to draw the circuit in LTSpice then simulate it.

Cheers

Ian

Above is a NETLIST.

Below is a SCHEMATIC.

Here are some discussions of netlist-to-schematic conversion...

None that I know of actually work well.

The above netlist is simple, translate it by hand ;-)

Also, I am SURE that there is some way to import a netlist into LTspice _without_ having to translate it to a schematic.

LTspice users? ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

LTspice is very compatible with PSpice netlists. When you do a File>Open in LTspice, be sure you select Netlists as the file type.

To make life easier, take the PSpice netlist and draw a schematic from it in LTspice. It's such a small circuit that you should be able to do this in 10 minutes.

--
Mark

"petrus bitbyter" schrieb im Newsbeitrag news:4b4310ea$0$7031$ snipped-for-privacy@dreader32.news.xs4all.nl...

Hello Petrus,

You could directly run the netlist if you comment the .AC and the .Graph line. Below is this netlist file "test4.cir". It's ready to be used with LTspice.

• Netlist generated by ActiveLP

• --- Active Low-Pass Filter ----

• Filter Topologie: Sallen-Key

• Filter Type: Butterworth

• Filter Order: 3

• -3 dB-Frequency: 300 Hz V1 O0 0 AC 1 0 PULSE(0 1 0 33.333u 33.333u 33.333m)

• Ideal Circuit using Voltage controlled Voltage Sources RI1A O0 BI1 112.88 CI1A BI1 0 4.7u EI1 OI1 0 BI1 0 1 RI2A OI1 AI2 78.805 RI2B AI2 BI2 162.34 CI2A BI2 0 2.2u CI2B AI2 OI2 10u EI2 OI2 0 BI2 0 1

*.graph OI2 curveLabel="Output Stage 2 Ideal" nowarn=true ylog=auto

• Simulation Control .TRAN 0 66.667m 0 33.333u

*.AC DEC 1k 3 3k

I have additionally made a schematic of this netlist. It is 100% equivalent to the original netlist. Schematic file "test4a.asc".

Best regards, Helmut

Version 4 SHEET 1 1308 680 WIRE 768 -16 592 -16 WIRE 912 -16 832 -16 WIRE 32 80 0 80 WIRE 80 80 32 80 WIRE 224 80 160 80 WIRE 240 80 224 80 WIRE 336 80 240 80 WIRE 400 80 384 80 WIRE 448 80 400 80 WIRE 560 80 528 80 WIRE 592 80 592 -16 WIRE 592 80 560 80 WIRE 640 80 592 80 WIRE 752 80 720 80 WIRE 768 80 752 80 WIRE 864 80 768 80 WIRE 912 80 912 -16 WIRE 976 80 912 80 WIRE 0 144 0 80 WIRE 240 144 240 80 WIRE 384 144 384 80 WIRE 912 144 912 80 WIRE 336 160 336 80 WIRE 864 160 864 80 WIRE 768 176 768 80 WIRE 0 288 0 224 WIRE 240 288 240 208 WIRE 240 288 0 288 WIRE 336 288 336 208 WIRE 336 288 240 288 WIRE 384 288 384 224 WIRE 384 288 336 288 WIRE 768 288 768 240 WIRE 768 288 384 288 WIRE 864 288 864 208 WIRE 864 288 768 288 WIRE 912 288 912 224 WIRE 912 288 864 288 WIRE 0 304 0 288 FLAG 32 80 O0 FLAG 224 80 BI1 FLAG 0 304 0 FLAG 400 80 OI1 FLAG 560 80 AI2 FLAG 752 80 BI2 FLAG 976 80 OI2 IOPIN 976 80 Out SYMBOL voltage 0 128 R0 WINDOW 3 -34 220 Left 0 WINDOW 123 -32 246 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 0 33.333u 33.333u 33.333m 100m) SYMATTR Value2 AC 1 SYMBOL res 64 96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName RI1A SYMATTR Value 112.88 SYMBOL cap 224 144 R0 SYMATTR InstName CI1A SYMATTR Value 4.7µ SYMBOL e 384 128 R0 SYMATTR InstName EI1 SYMATTR Value 1 SYMBOL res 432 96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName RI2A SYMATTR Value 78.805 SYMBOL res 624 96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName RI2B SYMATTR Value 162.34 SYMBOL cap 752 176 R0 SYMATTR InstName CI2A SYMATTR Value 2.2µ SYMBOL e 912 128 R0 SYMATTR InstName EI2 SYMATTR Value 1 SYMBOL cap 768 0 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName CI2B SYMATTR Value 10µ TEXT 0 -40 Left 0 !.TRAN 0 66.667m 0 33.333u TEXT 0 -80 Left 0 ;.AC DEC 1k 3 3k

Hi Jim,

I'm not a SPICE expert but this is very easy. Insert a Text as Spice directive in the plain schematic and then run the simulation as is. In this example the line

.graph OI2 curveLabel="Output Stage 2 Ideal" nowarn=true ylog=auto

should be eliminated with a semicolon in the beginning. Also you have to decide whether you want to simulate .Tran or .AC

May be there is a more elegant way to do but this one is simple to use

Marte

See....

This is how I include a client's existing chip, or cell's the client has designed, without having to draw those sections with a schematic editor. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.