power dissipation in LT Spice

Apr 13, 2013 31 Replies

Well, it was originally written to speed up SMPS simulations, and appears to work hard around edges, and speed up on flat bits. Maybe there's some lookahead going on.

Being able to specify min timestep would be nice.

OTOH, I rarely, if ever simulate SMPS, so I'm not the target audience.

What I really would like is polar/Smith plots.

"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)

I want to make narrow pulses at low duty cycles, load powers well below 100 watts average, so fragmentation won't be a hazard. I'm figuring dpak or SO8 type surface-mount fets and *lots* of capacitors, low 10s of joules maybe.

It's at the idea stage now, just thinking about possibilities.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

Gnaw, with transistors these days, 7.5kW continuous is easy. Theoretically, 4 x TO-247 superjunction FETs will do that at up to a MHz. Pulses? That's childs play! ;-)

Tim

Deep Friar: a very philosophical monk. Website: http://seventransistorlabs.com

Pretty much. The issues become capacitors, packaging, and some way to get the drive to the load.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

That's what one guy thought as well. All my recommendations regarding steep drive and UVLO and all that were brushed aside. One fine day his drive supply must have cut out, slowly since there were electrolytics, and ... *PHOOMP*

Regards, Joerg http://www.analogconsultants.com/

Don't forget an UVLO on the gate drive. If you keep pulsing while that sags away a few hundred watts can migrate from the load into the FETs.

Regards, Joerg http://www.analogconsultants.com/

One has to do something to avoid a division-by-zero error in the MTBF calculation.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

written)

against

appears

Maximum time step is on the .options card.

?-)

against

I knew that, it was *minimum* timestep we were discussing.

"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)

I thought that the Max Timestep may be a misnomer, and actually means minimum timestep. The actual directive in LTSpice is as follows:

.tran 0 400m 10m 5u startup uic

Which is defined as:

.tran

There is a parameter in the transient analysis directive for timestep from

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.tran [Tstart [dTmax]] [modifiers] or .tran [modifiers]

It says: "Tstep is the plotting increment for the waveforms but is also used as an initial step-size guess. LTspice uses waveform compression, so this parameter is of little value and can be omitted or set to zero."

Here is something I found in

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  1. Gminsteps (DC Convergence) Example: .OPTIONS GMINSTEPS=200 The Gminsteps option adjusts the number of Gmin increments that will be used during the DC analysis. Gmin stepping is invoked automatically when there is a convergence problem. Gmin stepping is a new algorithm in SPICE 3 that greatly improves DC convergence.

I tried various values of GMINSTEPS in LTspice but there seemed to be no

effect on simulation time.

Some other discussions of timestep:

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I have confirmed that the simulation can be slowed down and made more accurate by reducing the maxstimestep, while setting the Tstep or Tprint

value seems to have little or no effect.

Paul

written)

against

I don't think I've ever run across a setting for _minimum_ time step, only maximum. Setting a minimum would be asking for trouble... it could miss fast events... as LTspice has been demonstrated to do when operated in "fast" mode. ...Jim Thompson

| James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

written)

accuracy against

appears

some

Oops. IIRC it is on the options card as well.

?-/

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