Ping Hobbs: JFET Noise

BTW Anton, the original expression referred to knocking someone unconscious--'lights' referring to eyes. "Put his lights out" is a related expression.

Cheers

Phil "generally peaceable except to transistors" Hobbs

Is the file Philips.njf somewhere?

--

-TV

Oh sorry, I should have included the model instead.

Here it is: .model JBF862 NJF(Beta=47.800E-3 Betatce=-.5 Rd=.8 Rs=7.5000 Lambda=37.300E-3 Vto=-.57093 Vtotc=-2.0000E-3 Is=424.60E-12 Isr=2.995p N=1 Nr=2 Xti=3 Alpha=-1.0000E-3 Vk=59.97 Cgd=7.4002E-12 M=.6015 Pb=.5 Fc=.5 Cgs=8.2890E-12 Kf=87.5E-18 Af=1)

You can pick up the whole Philips.njf file (57kB) from .

Jeroen Belleman

Thanks!

Oh, now I understand the expression (thank you!), but still don't understand physics:( How do we bypass the emitter and why does it help us to get gain closer to 1.

The usual transistor current source puts a resistor R in series with the emitter, and applies some voltage V from there to the base. Thus as long as the transistor doesn't saturate, you get about

I =~ (V-0.7)/R

If you drop a volt or two across R, that greatly reduces the shot noise contribution of the transistor.

In this circuit, I want to modulate the current source via feedback. With a volt across R, I have to go another volt to double the current.

If I put a big bypass cap across R, then at high frequency the emitter is effectively grounded, so that to double the current I just have to go kT/e * ln(2) ~ 18 mV.

Cheers

Phil Hobbs

On 14/07/2016 08:31, Jeroen Belleman wrote:

Jeroen,

This is approx. the topology that Phil is describing (I just modified your cct)

Version 4 SHEET 1 3304 808 WIRE 192 -272 128 -272 WIRE 288 -272 192 -272 WIRE 432 -272 288 -272 WIRE 128 -240 128 -272 WIRE 432 -240 432 -272 WIRE 128 -128 128 -160 WIRE 128 -128 -128 -128 WIRE 128 -112 128 -128 WIRE 432 -96 432 -160 WIRE 512 -96 432 -96 WIRE 432 -64 432 -96 WIRE 432 -64 192 -64 WIRE 432 -16 432 -64 WIRE 512 -16 512 -96 WIRE 128 32 128 -16 WIRE -304 96 -368 96 WIRE -256 96 -304 96 WIRE 80 96 -256 96 WIRE 432 96 432 48 WIRE 512 96 512 48 WIRE 512 96 432 96 WIRE -368 144 -368 96 WIRE -256 144 -256 96 WIRE 288 160 288 -272 WIRE 432 160 432 96 WIRE 128 208 128 128 WIRE 224 208 128 208 WIRE 512 208 496 208 WIRE 32 256 32 224 WIRE -368 272 -368 224 WIRE -256 272 -256 224 WIRE -128 304 -128 -128 WIRE 432 320 432 256 WIRE 128 336 128 208 WIRE 32 384 32 336 WIRE 64 384 32 384 WIRE -128 416 -128 368 WIRE 32 416 32 384 WIRE 32 416 -128 416 WIRE 288 448 288 256 WIRE 368 448 288 448 WIRE 512 448 512 208 WIRE 512 448 368 448 WIRE 560 448 512 448 WIRE 624 448 560 448 WIRE 128 512 128 432 WIRE 224 512 128 512 WIRE 32 528 32 416 WIRE 128 528 128 512 WIRE 368 528 368 448 WIRE 32 640 32 608 WIRE 128 640 128 608 WIRE 128 640 32 640 WIRE 224 640 224 576 WIRE 224 640 128 640 WIRE 256 640 224 640 WIRE 368 640 368 608 WIRE 368 640 256 640 FLAG -368 272 0 FLAG -240 576 0 FLAG -352 576 0 FLAG 560 448 VOUT FLAG -352 496 VDD FLAG 32 224 VDD FLAG -256 272 0 FLAG 256 640 VEE FLAG 432 320 VEE FLAG -240 496 VEE FLAG 192 -272 VDD FLAG -304 96 VIN SYMBOL njf 80 32 R0 SYMATTR InstName J1 SYMATTR Value JBF862 SYMBOL npn 64 336 R0 SYMATTR InstName Q1 SYMATTR Value BFR92A SYMBOL npn 224 160 R0 SYMATTR InstName Q2 SYMATTR Value BFR92A SYMBOL res 112 512 R0 SYMATTR InstName R3 SYMATTR Value 100 SYMBOL voltage -352 480 R0 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL voltage -240 592 R180 WINDOW 0 24 96 Left 2 WINDOW 3 24 16 Left 2 SYMATTR InstName V2 SYMATTR Value 10 SYMBOL res 16 512 R0 SYMATTR InstName R5 SYMATTR Value 1k7 SYMBOL res 16 240 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL voltage -368 128 R0 WINDOW 0 -61 64 Bottom 2 WINDOW 3 -141 125 Bottom 2 WINDOW 123 44 124 Bottom 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value "" SYMATTR Value2 AC 1 SYMBOL res -272 128 R0 SYMATTR InstName R7 SYMATTR Value 1G SYMBOL res 352 512 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL npn 192 -112 M0 SYMATTR InstName Q3 SYMATTR Value BFR92A SYMBOL res 416 -256 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL cap 208 512 R0 SYMATTR InstName C1 SYMATTR Value 1 SYMBOL res 112 -256 R0 SYMATTR InstName R4 SYMATTR Value 100 SYMBOL zener 448 48 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D1 SYMATTR Value 1N750 SYMBOL cap -144 304 R0 SYMATTR InstName C2 SYMATTR Value 1 SYMBOL cap 496 -16 R0 SYMATTR InstName C3 SYMATTR Value 1 SYMBOL pnp 496 256 R180 WINDOW 3 53 68 Left 2 SYMATTR InstName Q4 SYMATTR Value BFT92 TEXT -392 -48 Left 2 !.ac dec 10 10 10G TEXT -392 -16 Left 2 !.lib Philips.njf

Hum yes, that explains a few little discrepancies between Phil's description and my interpretation. Yours is probably closer than mine.

I like my version because it's a little simpler and it's possible to tweak the gain to (1 +/- iota) by varying R2 or R3. A possible improvement would be to turn Q2 into another White follower, to drive lower impedance loads.

So many ways to build a follower. Isn't electronics fun?

Jeroen Belleman

Thank you for explanation, Phil!

JM, why can not we drive Q3 base from JFET's source through the capacitor? Do you afraid that Q3's biasing network would load JFET's source?

You need to modulate the current source with a signal proportional to the FET current. The collector of Q3 is the best place to monitor it since it's isolated from the FET and has the correct phase to modulate the current source (ie. if drain current drops Q3 collector rises thus Q1 base is pulled up to compensate).

or? Do you afraid that Q3's biasing network would load JFET's source?

That is obvious. I was asking about Q2+Q4. Why not just drive Q3's base from J1 source via c apacitor.

I do apologize, I misread your question as asking about Q1 base drive (which I did think was a rather odd question).

There's any number of ways of driving Q3 and all have their tradeoffs.

Jim,

Did the Sziklai diff pair idea go anywhere?

I've been digging through a bunch of old Tek and AD patents lately. Lots of folks seem to have liked combining Darlington/Sziklai pairs with current mirrors, but the window in parameter space where that helps seems to be pretty small.

Cheers

Phil Hobbs

I'm on hold waiting for the X-Fab modeling engineer to return from holiday. It appears I found an error in their NJFET Spice model... non-physical behavior... nothing like 18 years of chip design before I ever saw a simulator to make you trust your gut rather than a Spice model ;-)

See my recent post...

Subject: Sziklai Squared ?? Date: Wed, 20 Jul 2016 16:02:01 -0700 Message-ID:

for what I happened onto while working another part of the chip design. ...Jim Thompson