Our class-H thermoelectric cooler driver uses an LMR23630 sync buck regulator running off +5V and ground, synched to a 2.156 MHz clock, and with a buffered PWM controlling the set point. The feedback divider has three resistors: the usual two, which connect to the output and ground, and a third one from the buffer output. That lets the MCU vary the supply voltage from about 0.8V to 5V. (There's a few hundred millivolts of dropout at high current, so it never quite gets to 5V.)
Oddly, when the setpoint is above 4.7V, so the chip drops out of regulation, suddenly it starts oscillating at about 150 kHz with an amplitude of about 70 mV p-p. The waveform has a nearly triangular top and a rounded bottom. It speeds up a little when the load current increases.
What gives? Any wisdom gratefully received.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
I just browsed the datasheet... maybe you are going into pulse-skipping mode.
Page 16 shows operation in PFM mode, which is in the neighborhood of 150kHz. Page 12 describes user-selectable FPWM; since you want to sync at 2MHz, you have to allow pulse-skipping mode (if I read that right).
If that's not the issue, then maybe it's current into the FB node. Check the tabular data, page 9: 18us recovery from a power good glitch; since UV/OV block is fed from FB node, maybe you're sourcing too much current there? I doubt it but who knows.
I expected the FB loop to rail, as well-behaved loops do in such situations. A railed amplifier doesn't usually oscillate.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
The switching rate is still synchronized to the 2.15 MHz external clock. In this topology (extra resistive tap on the FB pin to dork the output voltage), there's not much opportunity for that sort of misbehaviour.
The FB pin is nominally at 1.0 V, and in the measurements I'm describing, the FB pin voltage was down by only about 12 or 15 mV from nominal.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
Me? Our loop compensation was tweaked on a breadboard, with the actual load capacitances, polymers and lots of ceramics, very low ESR. Our regs are absolutely going into burst mode at lowish loads. I should have anticipated this. Well, I didn't expect the FPGAs to use so little current.
I think TI deliberately uses high value dividers to keep apparent low-load efficiency up. That might explain the parallel cap across the upper feedback resistor.
I need a new regulator, a TPS54302 that stays in sync switch mode. Drop-in and more input voltage would be nice; I've asked someone to look for a part.
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
Yes to both. The loop gain is constant, because we're adjusting the output voltage by dumping current into the feedback node, not by changing the resistors. It's fine when programmed to 4.7V and oscillates above 4.75, just when the FB pin drops below 1V.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
It keeps on PWMing during the oscillation, at least at light load currents.
I agree. Fortunately this one (LMR23630FDRR) really truly PWMs down to zero load, and has external sync, so you can probably do the frequency dither externally.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510
http://electrooptical.net
http://hobbs-eo.com
To me, the behavior you describe looks like (at least not inconsistent with) subharmonic oscillation from loss of internal slope compensation.
Looking at block diagram in 8.2:
The feedback goes into an EA that is likely configured for a high output impedance. The type of RC compensation network indicated on the schematic is the one used for current output or for high impedance voltage output (equivalent to current output at non-steady-state conditions) EAs, with Cc effectively being an integrator capacitor.
A slope compensation signal (as required for stability) is added at this point. This is somewhat unusual as this approach can make the compensation signal susceptible to nonlinear effects. More typically, switching controllers will add slope compensation to the signal from the high side current sense circuit, on the opposite input of the PWM comparator.
We don't know how exactly TI made the addition of these 2 signals but with the EA output likely being a current output and with Rc being where it is, chances are that the slope compensation signal is also a current output signal, with Rc also being used for I/U conversion.
When the EA starts railing, there can be two separate unwanted adverse effects on stability (that I can think of, at least):
With the output from the EA being railed (assuming that its output impedance can be maintained in this state), the feedback loop loses its high frequency compensation (otherwise provided by Rc and HF gain of EA). The small signal AC gain of a railed amplifier is near zero, that multiplied by Rc is still near zero, so the HF compensation signal path drops out of operation. When the EA is only "slightly" railed (within mV of regulation), this could lead to an oscillatory behavior. With the loop on the border between going into and out of regulation, a lack of HF compensation can lead to the oscillation of the main control loop.
If the EA cannot maintain its output impedance when railed and the effective impedance driving the compensation network drops, the slope compensation signal may be forced to work against a low-impedance sink, possibly shunting out the slope compensation and dropping its signal level to where it can no longer provide its intended function. In this case it does not matter whether the culprit is the EA itself or any subsequent limiter stage designed to prevent Cc from overcharging by clamping it down. A clamping stage would be even worse, as when railed, it would have shorted out the slope compensation ramp entirely. If the controller could operate at 100% duty cycle, that obviously would not be a problem, but this one has a minimum off time, so keeps switching.
With the load being a high-current one (TEC), chances are that the peak current mode control still plays some role, especially if the minimum off time was implemented by some trickery (like adding an override pulse to the high side current sense signal rather than forcing the PWM FF off directly from the oscillator). If the chip internally still relies on the peak current mode control mechanism in some way (even in maximum duty cycle operation, where it should not need to) then a loss of slope compensation will make it susceptible to a subharmonic oscillation with the frequency being influenced by any resonances in the output circuit.
Normally, with the EA being "fully" railed, I also would not expect any oscillation. I'd expect a fixed ON time followed by a fixed OFF time, both reasonably stable. But with a high current load and with the EA only "slightly" railed, maybe some effects from a (now decompensated) peak current mode loop are coming through and messing up stability...
This may be testable by "fully" railing the EA by strongly overdriving the FB input - whether or not the oscillation then disappears.
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