Parasitics?

The current increase at shut-off is charge injection into base- collector junction.

If your problem only related to the pnp transistor, I'd say it was caused by charge storage. That you're having the same problem with a FET suggests another problem.

Perhaps you could provide the exact circuit you're using.

Sylvia.

Version 4 SHEET 1 2820 1128 WIRE 368 -272 144 -272 WIRE 512 -272 368 -272 WIRE 816 -272 512 -272 WIRE 1024 -272 816 -272 WIRE 1216 -272 1024 -272 WIRE 144 -224 144 -272 WIRE 368 -224 368 -272 WIRE 816 -208 816 -272 WIRE 512 -112 512 -272 WIRE 368 -96 368 -144 WIRE 416 -96 368 -96 WIRE 464 -96 416 -96 WIRE 816 -96 816 -128 WIRE 144 -64 144 -144 WIRE 192 -64 144 -64 WIRE 224 -64 192 -64 WIRE 368 -64 368 -96 WIRE 368 -64 304 -64 WIRE 512 16 512 -16 WIRE 592 16 512 16 WIRE 640 16 592 16 WIRE 800 16 720 16 WIRE 832 16 800 16 WIRE 896 16 832 16 WIRE 800 48 800 16 WIRE 800 128 800 112 FLAG 816 -96 0 FLAG 1024 -272 Vdd FLAG 800 128 0 FLAG 832 16 Bias FLAG 592 16 Fcntl FLAG 192 -64 Fout FLAG 416 -96 Gate SYMBOL voltage 144 -240 R0 WINDOW 123 -97 26 Left 2 WINDOW 39 -277 71 Left 2 WINDOW 3 -412 109 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=0.01 Cpar=1fF SYMATTR Value PULSE(0 3.3 3us 10ns 10ns 2us 8us 1000) SYMATTR InstName V1 SYMBOL voltage 816 -224 R0 WINDOW 123 24 132 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 24 102 Left 2 SYMATTR Value 3.3 SYMATTR InstName V2 SYMBOL res 624 0 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 4700 SYMBOL cap 816 48 M0 WINDOW 0 43 20 Left 2 SYMATTR InstName C1

SYMBOL res 320 -80 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL res 352 -128 M180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R6 SYMATTR Value 100k SYMBOL pmos 464 -16 M180 SYMATTR InstName M1 SYMATTR Value BSS84 TEXT 304 160 Left 2 !.tran 6ms TEXT 304 96 Left 2 !.options plotwinsize=0 TEXT 32 96 Left 2 !.ic V(Vf)=1.61\n.ic V(Bias)=2.7 TEXT 304 128 Left 2 !.PARAM Tol = 1.0

When you try to drive the gate high, the gate-drain capacitance has to be charged, and the only way than can happen is for current to flow through R3. A back of the envelope calculation suggests that will take about the time you're seeing.

To get it to switch more quickly, you need to reduce R3, or provide some other path for the current.

A diode in series with R3, and a 1K resistor from the drain to ground improves things substantially.

Sylvia.

That actually makes things worse by substituting the capacitance of the diode through the 1k resistor for the capacitance of the transistor.

I was trying to use a very low power approach by injecting charge onto a capacitor which would have a very low drain from it. But if low value resistors have to be added, I can just use a dithered pullup/pulldown instead. That may also have current injection, but it should be approximately equal in both directions because of the push-pull output.

I had in mind this. The current through R3 reverses, then returns to zero in 190ns.

Version 4 SHEET 1 2820 1128 WIRE 368 -272 144 -272 WIRE 512 -272 368 -272 WIRE 816 -272 512 -272 WIRE 1024 -272 816 -272 WIRE 1216 -272 1024 -272 WIRE 144 -224 144 -272 WIRE 368 -224 368 -272 WIRE 816 -208 816 -272 WIRE 512 -112 512 -272 WIRE 368 -96 368 -144 WIRE 416 -96 368 -96 WIRE 448 -96 416 -96 WIRE 464 -96 448 -96 WIRE 816 -96 816 -128 WIRE 448 -80 448 -96 WIRE 144 -64 144 -144 WIRE 224 -64 144 -64 WIRE 368 -64 368 -96 WIRE 368 -64 304 -64 WIRE 512 -16 512 -48 WIRE 512 16 512 -16 WIRE 544 16 512 16 WIRE 640 16 608 16 WIRE 800 16 720 16 WIRE 832 16 800 16 WIRE 896 16 832 16 WIRE 512 32 512 16 WIRE 800 48 800 16 WIRE 800 128 800 112 FLAG 816 -96 0 FLAG 1024 -272 Vdd FLAG 800 128 0 FLAG 832 16 Bias FLAG 608 -32 Fcntl FLAG 416 -96 Gate FLAG 512 112 0 SYMBOL voltage 144 -240 R0 WINDOW 123 -97 26 Left 2 WINDOW 39 -277 71 Left 2 WINDOW 3 -412 109 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=0.01 Cpar=1fF SYMATTR Value PULSE(0 3.3 3us 10ns 10ns 2us 8us 1000) SYMATTR InstName V1 SYMBOL voltage 816 -224 R0 WINDOW 123 24 132 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 24 102 Left 2 SYMATTR Value 3.3 SYMATTR InstName V2 SYMBOL res 624 0 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 4700 SYMBOL cap 816 48 M0 WINDOW 0 43 20 Left 2 SYMATTR InstName C1

SYMBOL res 352 -240 R0 SYMATTR InstName R1 SYMATTR Value 10K SYMBOL res 496 16 R0 SYMATTR InstName R2 SYMATTR Value 1K SYMBOL diode 544 32 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value 1N914 SYMBOL res 320 -80 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 1K SYMBOL pmos 464 -16 M180 SYMATTR InstName M1 SYMATTR Value BSS84 TEXT 304 160 Left 2 !.tran 20E-6 TEXT 304 96 Left 2 !.options plotwinsize=0 TEXT 32 96 Left 2 !.ic V(Vf)=1.61\n.ic V(Bias)=2.7 TEXT 304 128 Left 2 !.PARAM Tol = 1.0

Yes, that's what I modeled. I see large current spikes on both edges of the pulse. Regardless, I won't be using a discrete transistor. I'll be using the output from an FPGA. Depending on the pulse width of the output, the current in R2 is around 1 mA which is as much as the entire rest of the project.

I can use a large resistor in series with the output into the cap and drive it high and low for a range of duty cycles. That will get me what I need. This circuit only needs to source voltage, so I thought it would use less current to only pull high. We'll see what the real circuit does when I use the actual FPGA output. It doesn't have to be perfectly linear with duty cycle, but it does need to at least be monotonic.

Well gee, it's a simulation, you don't even have to clip instruments onto the thing to see the current and voltage everywhere!

If you look at the V and I versus time, at the collector, you will see that Ic / (dVc/dt) is proportional to Ccb. In other words, the transistor is off, and the capacitance is being charged through the 47k resistor.

Simple solution: remove the charge!

Connect collector directly to the load. To set charge current, shove a resistor between +V and emitter.

Now you have a transconductance stage: voltage in, current out. Or, with a resistor from +V to base, a current mirror (current in, current out). Or a diode-strapped transistor plus a resistor (same thing, less drift and offset).

You still get some charge injection because of the base voltage moving (because it's Ccb, not just C to +V). This can be reduced by using a relatively small emitter resistor (for, say, 0.1mA output, you only need to tug on the base by 0.1V, if you use a 1k resistor). Or it can be isolated by cascoding the collector current with a second transistor (whose base voltage is fixed somewhat below the lowest base voltage you want to use on the first transistor).

HTH,

Tim

Isn't that what I said, its the gate-drain charge?

Thanks for the info. I'm not actually building a circuit from discretes. So I'll just use a voltage source to model this for now and check it on the bench.

A nanocoulomb in a microsecond is a milliamp.

How about an ATF55143 ePHEMT?

Cheers

Phil Hobbs

Cue J.L.

Uh-huh, and what is the problem you can't simply drive this flea power RC from the FPGA directly? You do know how an RC works? Right?

I'm not sure what you are talking about. I will be driving the RC directly from the FPGA output.

I don't have FPGA outputs in the simulation, so I was using a FET as a model. Since it appears there are issues with charge injection when driving a high impedance, I will just have to work that out on the bench.

Huh? You think that circuit is representative of an FPGA CMOS output? Don't think so...

First order approximation, a FET. I'm not going to try to model it more closely. There's not much I can do with it other than vary the drive strenth/slew rate. So as I said, I'll test it on the bench and see what I can get out of it.

The FPGA CMOS output is likely to be push-pull, which will make a big difference.

Sylvia.

Push-pull is just a pair of FETs, one pull up and one pull down. There is also an enable so by setting the output low and toggling the enable, only one FET will be turned on and off. This is very commonly done to make the output an open drain or by setting the output to a high and toggling the enable the output is an open source.

In FPGAs they normally also have multiple FETs in parallel to alter the drive strength. So you can make it a stronger drive or a weaker drive although that can't be changed during operation, only by configuration. However, if you wish, you can wire multiple outputs in parallel with different drive strengths and in effect have a crude digital to current output of very low resolution and accuracy. I never thought about this before but since each output can be high or low, a trinary code could be used. I see drive strengths scaling by 1, 2 and 3. So by combining three outputs of different strengths you could achieve sums of all integers from -6 to 6, 13 values. Hmmmm...

The configuration avoids trying to get the gate charge through your load.

Sylvia.