Yes, that works perfect. It saves a lot or work..
I still don't understand why they don't set the "BVbe" in the models? It can really lead you off the deep end in the real world when transposing it over.
I do understand not setting the "BVcbo" parameter, the person behind the design should know better but, forgetting to set the "BVbe" can lead to some misfortune as it would not be immediately obvious.
Thanks
Jamie
I do. In IC design, breakdown voltages of transistors (Vbe, Vce etc Vgs) are rarely set, because one wants to know by default what will happen in the circuit when not in breakdown. Bv can vary by a huge amount, e.g. gate oxide from say 8v to 15v, so a one off value causes problems.
To get around the issues you mention, PDK kits are set up with limits verification. A the simulation progresses the output file will show over voltages and over currents (melt) in any device. Its called SOAC - Safe Operating Area Check. Modelling breakdown actually hinders circuit evaluation. The only BV that I would want set it that of a Zener diode, i.e. designed to run that way.
Kevin Aylward
Yep. I even have a macro in PSpice Probe that displays SOAG (safe-operating-area-gate) for super-small feature-size MOS devices. ...Jim Thompson
On Thu, 11 Sep 2014 18:07:50 +0100 in sci.electronics.design, "Kevin Aylward" wrote,
Does that include LTSpice models for LT chips?
I don't know about LT, but Analog Devices' modeling department is run by a VP of MARKETING... draw your own conclusions >:-} ...Jim Thompson
That makes no sense to me. well, maybe for BVceo but for the BVbe. I think it's very important that the sim behaves and displays the effects of the base and emitter breaking down with in the circuit, which will give the circuit a totally different out look of how it's going to work in real life.
There are many times where the circuit may zener the BE, if not constantly, briefly. Either way it would be nice to see this defect that is deep in the circuit. I dug up some scrap circuits I have in a junk folder that were posted here over the recent years since I've started to use a simulator and I found a couple that fail if you set the BVbe to it's value. That's just an example of parms that shouldn't be ignored.
That's just my opinion I guess. I'll say no more but this, I am now going to set that parameter in case I think it maybe important in cases where voltages may get much higher than Vbe in the circuit.
Jamie
Datasheets are marketing documents nowadays, so I'm not surprised.
Cheers
Phil Hobbs
In makes perfect sense, that's why all the hundreds of billions of ics are designed without breakdown modelled, and use SOAC instead.
The device will never break down in real life, because the circuit, using the SOAC results, is designed to never overvoltage. For example, if the real signals are clamped, you cant easily tell if its 200 mv over voltage or 5 volts. The signals need to be free to do what they will do without being clamped.
The real signals tell you that a designed clamp is required, for example, letting a real base emitter junction overvoltage can destroy its noise performance,and significantly reduce its gain. If this is flagged up by SOAC one knows to put a reverse diode across the base emitter.
It's absolutely key in ic design that devices are always operated in their SOA. Its part of the tapeout sign off procedure.
Kevin Aylward
Yep. latest from LT. Marketing Head line:
LTC2000 - 16-/14-/11-Bit 2.5Gsps DACs
Immediately obvious, that this head line is a lie. That is, a lie being something deliberately designed to hide the truth.
A 16 bit 2.5 Gbs device should be 1/2 lsb accurate, at at input frequency of
1.25 GHz. Wading through the data sheet, resuts in the conclusion that, even if steady state testing were valid, te part hits at about 8 bits of true accuracy.Kevin Aylward
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