Odd behavior of LTSpice for NMOS and PMOS in series with zero gate voltage

P E Schoen · 2017-11-11T04:28:33+00:00

I have been working on an analog multiplexer using discrete NMOS and PMOS devices. I have the gates connected to their respective sources through resistors and their drains are connected together. Positive and negative voltages are applied from source to source through a series load resistor. The NMOS works as expected - the body diode conducts when a negative voltage is applied and it blocks for positive voltage. But the PMOS device conducts when it should block. Here is the ASCII file for a simple test that shows this odd behavior. A screen shot of the simulation: I have tried this with several models of the PMOS device. I also closed and re-opened LTSpice. Am I not understanding PMOS devices or is something strange going on? Thanks, Paul

Nov 11, 2017 21 Replies

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piglet 8 years ago

Could be a typo, 2uF for 20uF or 90VA for 9VA

piglet

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John Larkin 8 years ago

Silly typo, that nobody caught. Everybody knows that 1 uF is 2600 ohms at 60 Hz, and 1 pF is 160 ohms at 1 GHz.

John Larkin Highland Technology, Inc lunatic fringe electronics

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