New software of Karnaugh Maps

Karnaugh Studio

And then there's

KarnaughMap v4.4.5 (up to 5 variables)

by Russell Sasamori

DOESN'T require IE or JavaCrap

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

karnaugh Studio in it's full version, can minimize from 2 - 12 variables and there would be a new version comming soon for linux

Or just draw things the way they're easiest to understand, and then let the FPGA compiler optimize it.

John

The difference of this product with other in him market, is that the method and the algorithms of simplification are own technology and we are presenting it. The next product will be minimize 30 Variables.

Did you reinvent Quine-McCluskey?

Why? No one outside of college minimizes logic, at least in the classical sense.

The implementation of algorithms known Quine-McCluskey only minimize up to 25 variables and I have simplified 30 and already I go towards the 60 variables.

I know the Algorithms Quine-McCluskey and Espresso Exact and I dont reinvent Quine-McCluskey.

I didn' tknow Quine-McCluskey was limited at all. That was never taught, perhaps because no one actually does logic minimization in the real world. In the thirty five years or so since I was introduced to these things in college I've only done minimization of more than three or four variables, for college coursework. ...never in practice.

Why?

...and why don't you learn how to post, while you're at it?

Right. I've never used a k-map. Given the realities of available gate types, the desirability to maintain clarity, and, nowadays, FPGA architectures and their compilers, it isn't all that useful. And anybody who does a lot of logic design can pretty much minimize, as far as he cares to, by inspection.

John

Classical minimization also assumes unrealistic gates and a single output of n-variables. It falls apart when constrained to gate fan in/out and multiple equations are involved. IOW, when reality sets in.

As you say, synthesis does the hard work these days.