mux-friendly opamp

Datasheet says cascaded. Cascode is more correct

Correction : the lower one is the RF input and also sets the bias current. So it has to be AC coupled to the input signal. See Fig. 45 of the datasheet

A broadband amplifier with response from DC to 48 GHz. The AC coupling at the input and output loses the DC value of the input signal, so I need a composite amplifier with an RF path and another one for the DC path.

In a book from either Bob Pease or Jim Williams there is a section on scope input design that shows exactly this.

cheers, Gerhard

I first saw it in an HP Journal article from the 1970's. But thanks for the note. I will look it up and see if it says anything about phase bumps at the crossover frequency.

Do you want the gain to be without DC offset? 0 in makes 0 out?

You could just shift the supplies to center the output, and then add a little DC offset at the input.

The art & Science of analog circuit design, ed. Jim Williams Butterworth-Heinemann ISBN 0-7506 9505-6 / EDN

Chapter 7, Steve Roach. signal conditioning in Oscilloscopes & the spirit of invention.

It's the common input scheme in oscilloscopes; one could just slvishly copy the design (and feed some broadband signals in, and look for difference between delay-line and amplified-then-attenuated paths in a test jig, to trim the phase at cutoff.

One example of the scheme is here: page 40, 'vertical preamplifier' shows feedback fo the op amp ( LF gain ) from the summed output, and a trim is required for the HF (FET) contribution.

Thanks. I found it at

Not exactly the same. In my case, the RF path has to be AC coupled so it needs a LF path for the DC.

Thanks. The feedback is to offset the trace on the screen. I need to preserve the DC value of the input signal with minimal offset.

The input and output of the RF path is capacitive coupled. The input has a bias voltage to set the current, and the output is at VDD through a bias T.

So I can't shift the supplies to center the output.

Don't capacitively couple the output.

John Larkin wrote:

No choice. I have to reintroduce the DC offset of the input signal, otherwise it will be shorted to VDD by the inductor connected between VDD and the mosfet drains.

Here is the much requested sketch

Version 4 SHEET 1 1204 680 WIRE 496 -400 464 -400 WIRE 560 -400 496 -400 WIRE 560 -384 560 -400 WIRE 560 -288 560 -304 WIRE 656 -288 560 -288 WIRE 768 -288 720 -288 WIRE 832 -288 768 -288 WIRE 880 -288 832 -288 WIRE 560 -272 560 -288 WIRE 432 -192 400 -192 WIRE 512 -192 432 -192 WIRE 560 -160 560 -176 WIRE 768 -128 768 -288 WIRE 112 -80 80 -80 WIRE 192 -80 112 -80 WIRE 288 -80 192 -80 WIRE 416 -80 352 -80 WIRE 512 -80 416 -80 WIRE 416 -64 416 -80 WIRE 560 -48 560 -64 WIRE 192 32 192 -80 WIRE 368 32 352 32 WIRE 416 32 416 16 WIRE 416 32 368 32 WIRE 448 96 288 96 WIRE 656 96 528 96 WIRE 768 96 768 -48 WIRE 768 96 656 96 WIRE 288 192 288 96 WIRE 368 192 288 192 WIRE 656 224 656 96 WIRE 656 224 592 224 WIRE 192 256 192 112 WIRE 368 256 192 256 WIRE 192 288 192 256 WIRE 288 288 288 192 WIRE 192 368 192 352 WIRE 288 384 288 368 FLAG 560 -48 0 FLAG 496 -400 VDD FLAG 368 32 VBias1 FLAG 432 -192 VBias2 FLAG 192 368 0 FLAG 112 -80 Input FLAG 832 -288 Output FLAG 288 384 0 SYMBOL cap 352 -96 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value "" SYMBOL res 400 -80 R0 SYMATTR InstName R1 SYMATTR Value "" SYMBOL nmos 512 -160 R0 SYMATTR InstName M1 SYMATTR Value "" SYMBOL nmos 512 -272 R0 SYMATTR InstName M2 SYMATTR Value "" SYMBOL ind 544 -400 R0 SYMATTR InstName L1 SYMATTR Value "" SYMBOL cap 208 352 R180 WINDOW 3 24 -7 Left 2 SYMATTR InstName C2 SYMATTR Value "" SYMBOL ind 752 -144 R0 SYMATTR InstName L2 SYMATTR Value "" SYMBOL res 176 16 R0 SYMATTR InstName R2 SYMATTR Value "" SYMBOL cap 720 -304 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value "" SYMBOL res 272 272 R0 SYMATTR InstName R3 SYMATTR Value "" SYMBOL res 544 80 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value "" TEXT 344 -488 Left 2 ;'DC to 48 GHz Amplifier TEXT 384 192 Left 2 ;- TEXT 376 256 Left 2 ;+ TEXT 280 -144 Left 2 ;High Pass TEXT 80 64 Left 2 ;Low Pass LINE Normal 592 224 368 128 LINE Normal 368 304 592 224 LINE Normal 368 128 368 304

Jim Williams left us many examples and tips.

Cheers, James Arthur

Get rid of L1, C3, and L2. Connect the output to the load. Bias up everything (Vdd and ground) for nominal zero output voltage.

Now you just need to add some input offset.

Incidentally, Qorvo has some fast packaged distributed amps. But you need an NDA to see their data sheets.

Not so simple. VBias1 sets the HMC1022ACHIPS bias current. The datasheet specifies 150 mA. With VDD set to zero volts, VBias1 will be -8 to -10 Volts. C1 is required to allow input signals at 0V, so the input AC coupling does not allow response down to DC.

The datasheet shows some pretty stringent requirements for mounting the chip. I would be concerned about lifting the chip off ground might lead to serious oscillation problems, or at least peaking at some point over the 48 GHz bandwidth.

Correction: -10 to -12 Volts.

Did you work at Byberry Rd? m

snipped-for-privacy@yahoo.com wrote in news: snipped-for-privacy@googlegroups.com:

GI's sat uplink encoder division was in Sorrento Valley, CA.

Lusk Blvd.