Mixed lead/non lead soldering

Correct, peak temp is max(solder1, solder2). The mixed alloy will leave a matte deposit but should be okay, give or take whatever issues a matte finish gives rise to.

Tim

There is a whole dedicated subindustry for reballing BGA for the RoHS derrogated industries of medical,nuclear,military and aerospace, that require proper reliable soldering. If you can mechanically scrape off the solid tin of all other components , including likes of RoHS spec resistors, and re-"tin" you will much improve long term reliability

It does work fine - but I don't do it with BGAs.

NT

Can't you wipe the current BGA balls off their pads and re-ball with leaded solder balls?

I checked with my mfg guys. When they solder a lead-free BGA, using tin-lead solder paste, they use the normal tin-lead temperature profile, which peaks below the official melting point of the balls. So we're soldering to the balls, not melting them.

Several million balls have been soldered this way with no problems.

I suspect that the tin balls dissolve a bit into the solder anyhow. They do look sort of flat on the bottom, as if they dissolved or melted a bit.

As one guy pointed out, we don't bother to melt the copper, either.

Ding! Light comes on.

Thanks, that sounds reasonable. What concerns me a bit is what they say about this method:

Use standard pre-heat ramp and temperature profile as if you were using crappy SAC. Result will be an alloy that has MP near tin-lead. Do not bump or shake when hot as parts may drop off; liquid tin-lead at those temps may act like thick honey..

It's still not a good idea. The ball collapsing causes the chip to self-center on the pads. You'll probably get away with it because you have a pile of solder paste on the pads already but that's not the way it's designed to work.

I would hope not. ;-) It's a different issue.

It seems to work. Some of our aerospace customers want tin/lead, some customers demand RoHS, and we wouldn't want to stock two varieties of one FPGA, even if they were available in tin/lead.

We have an essentially zero defect rate on BGAs. Fine-pitch j-leads are a lot trickier. Everybody hates US8 and QFN things.

I just managed to solder a US8 package LVDS chip, by hand, all by myself. It was pretty awful. I globbed it over and then wicked away most of the glob.

(It's a FIN1101, a pretty amazing part; basically a 1 ns rri comparator for 85 cents. But it wouldn't do what I wanted it to do.)

I'm surprised they allow mixed metallurgy at all.

At the PPoE they (D/QFN) were a problem but that was completely fixed with a decent oven and tuning the process properly. Wettable flanks help a lot, too. Most manufacturers are going to them, now.

Use paste and a heat gun.

Then not worth the money. ;-)

Ugh, PDFN/PSON/PQFN. The few times I've seen them, they weren't labeled as such -- most notably an FTDI part. Very thin web of plastic around the outside, enclosing the bottom contacts' perimeter. Without a magnifier, you'd never know. But the solder knows, and you get blobs outside, instead of toe fillets.

Done properly, they're fine; just follow LGA rules (+/- 0.00mm land to pad size). No easier to inspect, though.

I rather like QFNs, given what they are. The solder joints are almost impossible to muck up; in fact I recently had to /add/ a short between pins on a device, and couldn't do it. Perfect fillets, all the time, even when you don't want it!

Tim

We don't ask permission. They want "COTS", so they get it.

I need a high frequency (~~100 MHz) differential triangle wave, so I had the brilliant idea of hanging a cap across the LVDS outputs and letting the internal current sources slew it up and down. Didn't work very well. People are largely silent about what's actually inside LVDS drivers, and my mental model turned out to be wrong.

Still, I learned a bit about other aspects of the chip, and I got to solder and measure and stuff for a while.

If they are ok with COTS, why are you doing leaded solder paste at all?

That's why wettable flanks have become so popular. Without them, the process resembles a BGA process and XRAY inspection is usually required. As you point out, with the wettable flanks the filets are easy to see. Most suppliers have gotten the message.

They should self-center just like a BGA.

Not all QFNs are created equal, though I, too, like them. At the PPoE we had a lot of trouble with them but most was self-inflicted.

This one is (relatively) nice. The data sheet claims that the pins are

That's got the wettable flanks, too.

Valid point.

Hell, at one customer, I haven't released a single PCB drawing that specified any other than "RoHS (2004) compliant".

Useful though it is, lead has gone the way of special-purpose applications only. If they wanted COTS, they should've maybe thought about it a little harder and reconsidered. :-)

Tim

Since you've purchased parts (I assume?): do they actually?

The tolerance is +0/-0.05mm, so it can be flush. (See "ALL FEATURES" note, C datum; that measurement, which the IPC calls "A1", is relative to C.)

The pad face region is 0.05-0.1mm tall, which isn't much (you probably wouldn't go with a traditional full IPC 0.35mm toe fillet), but still nonzero, and enough to see and use.

Their suggested footprint gives 0.1mm min toe (maybe 0.25 max, including PCB errors), which isn't really to IPC spec, but with so little height, I'm fine with that.

I rather like the tight tolerances on this part, even the exposed pad. I've seen QFNs with lazy 0.2, even 0.3mm tolerances. Some manufacturers are just

I recently placed an SMT coin cell holder, that indicates absolutely no tolerances on any dimensions, beyond the 0.3mm default in the title block. If you take the drawing literally, the bottom side alignment pegs are literally 100% useless. Whether real parts are that bad, is anyone's guess...

Tim