LVDS line receiver with an unencrypted SPICE model?

Does the spec sheet say anything about how it works so that a model could be made ? Block diagram or something ?

boB

Too much like work—it’ll be much easier to build the circuit and measure it. I can simulate most of the fast stuff, because it’s all discrete.

Thanks

Phil Hobbs

What sorts of risetimes and swings do you want?

I haven't used the FIN1002, but we've used several similar LVDS receivers and all seem to work like decent RRIO comparators. You can put an RC ramp into one input and a DAC into the other and make a ps-resolution programmable delay.

I've given up on fast linear ramps... too much work. An RC with a bit of polynomial DAC correction works great.

I have sent you a link.

I’m planning to use some fast gain to sharpen up the edge, probably a BFP740. It won’t have much chance to oscillate, so it should be fine.

You have to be a bit careful, because the prop delay depends some on the CM voltage. It’s a bit like the offset voltage of a RRIO op amp—squirrely things happen within a couple of V_BEs of one rail.

Cheers

Phil Hobbs

Thanks, John! We'll see if LTspice can digest it.

Cheers

Phil Hobbs

The LVDS receivers that we use do behave much better when the inputs are a volt or so below Vcc.

But we just poke in a bunch of DAC voltages, measure the delay times, and calculate a polynomial. Ramp curvature and cmrr don't matter much anymore.

Take a look at the SY88022 laser driver chip. It's stunning. Diff in, brutal but clean 25 ps outputs, smooth amplitude control down to zero, about $7.

Ah well, not unexpectedly LTspice puked its guts over the model syntax and the unsupported BSIM3 version 3.11.

I tried a few things, including changing it to call out BSIM 3.3, which LTspice claims to support, but no joy.

Back to behavioral. :(

Thanks again!

Phil Hobbs

Or slam one or two SAV541 types with the FIN output. They go from off to about 2 ohms in a few tenths of a volt of gate drive. The newer packages should have less wirebond inductance than the originals.

Package inductance probably dominates actual fast switching behavior. Spice models usually ignore that. I suppose that inductances could be inferred from s-params, but I couldn't do that.

Nice part, thanks.

For a SOT23, if you figure 0.7 nH in series and 1/4 pF to ground, you won't go far wrong. Leo Bodnar has gone upmarket, so I may need to start using them--I've used his stuff in POC protos, but not any more.

With SiGe BJTs running in normal bias, the real key is keeping the pad capacitance down. A good bead right at the base tames them very nicely at lowish drain current, but if you let the base pad capacitance get as large as 0.5 pF, above about 5 mA you're toast regardless of how good the bead is.

The nice thing about them for this job is that they cost $0.16 rather than $2. (Part of the royalty conversation is BOM savings.)

The business end of the TDR looks like a giant meat fork, with a slide hammer for getting it in and out of the ground. (Fortunately the circuit board is at the other end of a cable from the slide hammer!) It's got some sort of balun inside, which I hope is a bazooka-style one with ferrite, rather than something more complicated.

You really only care about suppressing the current on the outside of the shield. The classic bazooka is a 1/4-wave coaxial sleeve, shorted to the outer conductor at the generator end, so that it looks like an open circuit to any outside shield current.

It's pretty narrowband, of course, but a ferrite sleeve can do the job pretty well--all you really care about is that the outside shield current sees a high impedance, and the phase angle doesn't matter much.

Having control over both the TX and RX means that you can ignore a lot of stuff that real sampler designs have to worry about.

Cheers

Phil Hobbs

You can make a TDR that's coyote ugly, as long as it's fast, and deconvolve a software FIR filter to beautify it. And speed it up a bit maybe.

On 2024-07-05 16:05, john larkin wrote:> On Fri, 5 Jul 2024 15:52:20

-0400, Phil Hobbs

Are you, of all people, suggesting that we use that nasty evil ill-posed ill-conditioned _deconvolution_ thing you used to beat me up about?

Nah, must be my ear wax. ;)

Cheers

Phil Hobbs

Just tried it in LTspiff 24.0.11 and 17.0.36. It will run if you change value of R6 (about line 214) from 0.0 to something other than 0.0 (say 1e-12). (This with the subckt with package model.)

LTspice does ignore a lot of the BSIM parameters, but you get what you pay for...

If I can come up with a good online cal scheme, that's potentially a helpful method. I really don't want to have to be Agoston Agoston. ;)

But you can make things like blowby, nonlinear capacitance, poor sampling efficiency due to the diode R * sampling C time constant being too slow, and so on, go away.

This is done by (1) doing the second-stage sampling when nothing is going on at the input. That fixes the blowby problem.

Then (2), you feed back the second-stage sampled value to the sampling cap, which is the normal sampling loop approach.

Finally (3), you take 20 samples per delay value, so that the sampling loop converges, resulting in zero volts across the sampling bridge at the sampling instant. That gets rid of the nonlinear capacitance problem.

Cheers

Phil Hobbs

Me? Beat you up? I wouldnb't dare.

"Ill posed" means that academics don't approve. Tough, guys.

What sort of rise time are you after?

There are goofy possibilities.

For TDRing dirt, I find it hard to believe we'll need better than 100 ps.

Cheers

Phil Hobbs

Right you are, thanks!

Lots of warnings, but seems to do vaguely sensible things—220 ps rise, 300 ps fall, 1.5 ns delay.

Overall, probably closer than I would have got with a simple behavioral.

Cheers

Phil Hobbs

Here's an LTspud encrypted model if anyone wants it.