The 1G resistors keep the DC levels from wandering around. LT Spice txlines are kind of weird.
The caps represent LVDS receivers along the line. Every cap reflects, into every other capacitive load. As long as the ringing is moderate and symmetric, it doesn't seem to change the zero crossings.
-- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
Try 26nH (give or take ~2x) in series to each "pin". (Which uh, should be
13nH each side, since differential.) Or, say, a stub of 200 ohms and 130ps. Might have to remove ground under the stub.Source termination wouldn't hurt either, though for ECL I'm not sure if that would reduce signal level too much. A better pin model than an ideal voltage source would be wise. Likewise the input pins aren't going to be ideal capacitors. Maybe glean some hints from the IBIS model or something.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:
There's actually a small via at every pickoff. The diff pair is on the bottom and the receivers are on top.
I might enlarge the clearances between the vias and the planes, maybe extend the cutouts to the little stubs, but the 3 pF chip capacitance still dominates.
The inductors seem to make things worse.
ECL receivers would be better, but have nasty consequences. Reducing the line impedance would reduce the effects of the loading, but I'm already pulling down the ECL at its max current limit.
The zero crossings are what matter. They're not bad.
-- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
When I put a couple of ECLinPS receivers along a nominally 50R transmission line, I narrowed it down to get 75R in the vicinity of the receivers for long enough to compensate for the 1.3pF of the receiving pin.
It was back around 1997, and we were sorting out a 200MHz clock, so it was probably a complete waste of time, but it might be worth trying in your application.
-- Bill Sloman, Sydney
This is a somewhat better way to handle the DC issues.
I think a proper simulation of a differential pair requires three txlines.
-- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
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