If a gate drives a second gate differentiator, or generally if there is one supply, ESD current can't pull up the supply.
I haven't seen SCR latchup in a logic gate since the bad old days of CD4000A. I have seen it in some mixed-signal parts, like DACs.
There was one family of Xilinx parts that was really weird, but I recall it was some gross shoot-through hangup thing, not ESD latchup.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
I think that's a good start.
A saturating inductor, used as a pulse transformer, can take a quick rise (or fall) and, with a transistor drive, make it a short pulse. Just drive the base, with the transformer drive winding in series with the emitter, with a secondary winding to the base, and the transistor ON transition becomes rapid. Another secondary winding makes the logic-like output pulse.
mandag den 22. juni 2020 kl. 19.49.35 UTC+2 skrev John Larkin:
afair it the issue was that if the rise time of the supply was too slow it would get stuck half way
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If the voltage source is a capacitor being switched there is no reason to t hink it can't happen. Many oscillator designs use a series capacitor switc hed from the output so the other end drives far above and below the rails. A large series resistor is used to limit the input current to prevent latc hup.
Saying you haven't seen something happen is not the same as saying it can't or doesn't happen.
-- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
TI has a new logic series with schmitt triggers on all the inputs.
e.g.,
I burned up (literally) some early 'AC parts. I'd biased them linear for R.F. use, which they did. not. like.
Cheers, James
looks like that ic doesn't have the usual ESD diodes to ground and Vcc
more like a zener to ground
At Fig 8.3.3 I see a diode to ground, but nothing clamping positive spikes.
I think that's consistent with the part's 'Over-Voltage Tolerant Inputs,' which can't work as desired if clamped to Vdd.
Possibly not obvious in the schematic above is that Q1 doesn't saturate, which is kind of fun for reasons I can't quite put my finger on. It reeks of possibilities, though.
Cheers, James Arthur
Fig 10 is absurd. Right angles are barely visible with 30 ps TDR. Usually not at all.
This part will make a great RC oscillator, as long as you don't care what the frequency is.
Pretty bad data sheet, for 43 pages.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Before you attempt to design this, some more specs are needed.
Max Temp? max Vdd? Max load pF? Rise/fall time? jitter ?? (don't care?)
I'd vote for the XOR one-shot frequency doubler if skew was tolerable due t o asymmetry.
It would be very convenient to use a variation of a low power 4060 with the internal Astable clock and 14 bit counter to make a 1shot using Reset on t he last stage to generate something near a 100ns pulse. That might work for some at room temp, but probably too much pulse width variation with suppli er, Vdd & temp sensitivity.
That's why there's a huge advantage to swinging the timing cap--that makes it about a zilliondie times more predictable.
(The r-c timing cycle swings volts set by Vdd, instead of hundreds of mV determined by the gate's ill-defined hysteresis. And timing current is substantially proportional to Vdd, minimizing frequency drift.)
Cheers, James
snipped-for-privacy@yahoo.com wrote:
Thank you all for prompt and insightful your help; I did not expect such a fruitful discussion. This is very much appreciated!
The circuits by Bill and James inspired me to try the approach based on discrete parts. Especially the astable multivibrator by James can go as low as 400nA, which is just crazy. I would never believe that a BJT with
10 megaohms in its collector could perform any useful action at sub-volt input voltages, let alone in a reliable way. It was truly an eye-opener.Based on that, I tried to design something on my own, and the simulation is attached below. I have just built a prototype (but used BC849C instead of BC547C, as there is no model for the former) and it works exactly as simulated. The input current was measured with a Sanwa PC7000 and the frequencies/duty cycle with a DSO.
It oscillates in a very stable way starting from 0.6V (!!!), but it produces sort of a sine wave there (I_IN=160nA). At 0.7V, it becomes a pulser (477Hz), and at 1V, it is even a decent pulser (I_IN=340nA,
342Hz, duty cycle=7%). If the input voltage rises, the frequency goes down*, to 295Hz@1.4V (510nA, duty 3.55%). Then it starts rising with voltage, as expected. At 2.7V it is 1.04uA/514Hz/3%. At 3.3V it is 1.29uA/624Hz/2.5%. I have tested it up to 8V: 3.2uA/1474Hz/2.9%.*) What might be a reason for that?
This is the stage to be designed now. I will start with a simple RC differentiator placed between two inverters and see what happens.
There is no 123 in the AUP family.
Best regards, Piotr
Version 4 SHEET 1 1300 680 WIRE 144 -128 96 -128 WIRE 592 -128 224 -128 WIRE 720 -128 592 -128 WIRE 928 -128 720 -128 WIRE 720 -80 720 -128 WIRE 928 -64 928 -128 WIRE 96 -48 96 -128 WIRE 592 16 592 -128 WIRE 720 16 720 0 WIRE 832 16 720 16 WIRE 96 48 96 32 WIRE 928 64 928 16 WIRE 1056 64 928 64 WIRE 1152 64 1056 64 WIRE 720 96 720 16 WIRE 928 96 928 64 WIRE 480 144 400 144 WIRE 592 144 592 96 WIRE 592 144 480 144 WIRE 656 144 592 144 WIRE 832 144 832 16 WIRE 864 144 832 144 WIRE 480 192 480 144 WIRE 592 192 592 144 WIRE 720 208 720 192 WIRE 928 208 928 192 WIRE 592 288 592 256 WIRE 480 320 480 272 WIRE 1056 368 1056 64 WIRE 1056 368 544 368 WIRE 480 448 480 416 FLAG 720 208 0 FLAG 96 48 0 FLAG 928 208 0 FLAG 592 288 0 FLAG 400 144 V_CAP FLAG 480 448 0 FLAG 1152 64 OUT IOPIN 1152 64 Out SYMBOL npn 656 96 R0 SYMATTR InstName Q2 SYMATTR Value BC547C SYMBOL res 736 -96 M0 SYMATTR InstName R3 SYMATTR Value 10Meg SYMBOL res 608 0 M0 SYMATTR InstName R4 SYMATTR Value 10Meg SYMBOL res 128 -112 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R5 SYMATTR Value 1m SYMBOL voltage 96 -64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 3.3 SYMBOL npn 864 96 R0 SYMATTR InstName Q3 SYMATTR Value BC547C SYMBOL res 944 -80 M0 SYMATTR InstName R6 SYMATTR Value 4.7Meg SYMBOL cap 576 192 R0 SYMATTR InstName C1 SYMATTR Value 1000p SYMBOL npn 544 320 M0 SYMATTR InstName Q1 SYMATTR Value BC547C SYMBOL res 464 176 R0 SYMATTR InstName R1 SYMATTR Value 1m TEXT 6 112 Left 2 !.tran 10m TEXT 8 160 Left 2 !.IC V(V_CAP)=0
to asymmetry.
he internal Astable clock and 14 bit counter to make a 1shot using Reset on the last stage to generate something near a 100ns pulse. That might work f or some at room temp, but probably too much pulse width variation with supp lier, Vdd & temp sensitivity.
Why use the doubler? Firing the 100ns pulse off one edge avoids unnecessarily adding that dependence on the oscillator's symmetry, and might save power too, depending on the topology. (e.g. in Piotr's gate-version, only the rising r-c edge has the power-dissipating slew problem.)
Cheers, James Arthur
60C
3.6V max., 2.7V typ., then as low as you can go.
The load would be a 3mH inductor in series with a 33kOhm resistor.
Don't care. I am just checking if the pulse can make its way through the inductor and latch the answer in an SN74AUP1G80. The pulse is both the input and the clock to the FF -- a self-synchronous detection. Works like a charm, but the simplistic oscillator belts down enormous amount of power. I can spend only 10uW or so.
Best regards, Piotr
Yes, this is my beloved but never used part. I much adore the negative resistance devices. Four NE2-s sitting next to an FPGA is my current record.
But there are no SMD variants and the wanna-be replacement (the PUT) requires too many parts compared to an alternative solution.
Best regards, Piotr
Don't know if this is relevant:
Some schmitt triggers are designed for lower rail currents when the input is at the threshold point
About the oscillator, I have used very low current astable oscillator as mentioned elsewhere in the thread. Only thing that worries me a bit is using very high resistance value resistors, sensitive to leakage effects
Cheers
Klaus
One of the 74HC4060 data sheets (TI I think) showed an analysis of that app roach over variations in threshold. The frequency varied only something li ke 10 or 20%. Not much more than the cap itself. As the threshold moves, one phase gets longer and the other shorter.
I can't find that data sheet now. This is one of those parts that were bou ght and sold as part of companies and the data sheet may not have been a TI part initially. I found three different parts at TI, all CMOS 4060 device s. None of them have that analysis.
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using any class of CMOS for the Schmitt Inverter low frequency clock and the XOR monopulse f doubler with only 3.6V logic IC's for speed.
Simulated here
Where did you get the parameters for the Schmitt input on the inverter? You've set the high and low thresholds to 2 and 1 volt.
Should I assume you picked those numbers from air? This simulation doesn't consider the power supply current.
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On Monday, 22 June 2020 21:08:25 UTC-4, Anthony Stewart wrote: The classic BJT Astable has its limitations for asymmetry impedance and slow rise times can hurt the next stage if linear idle current increases in between Vdd~Vss
But it can operate < 2uA easily.
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